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HPEC 2006 Proceedings

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19 September
  Welcome
Eric Evans / MIT Lincoln Laboratory
Presentation
  Keynote Address – The Past as Prolog
Anita Jones / University of Virginia
Biography Keynote Speech
  Session 1: Novel Hardware and Device Technologies
Richard Linderman / AFRL
Focus 1: FPGA/ASIC Systems Technologies
David Cousins / BBN
 

Stream Architecture and
Programming
William Dally / Stanford University

New Process Technologies – Will Silicon CMOS Carry Us to the End of the Road Map?
Craig Keast / MIT Lincoln Laboratory
Presentation

MONARCH: A First Generation Polymorphic Computing Processor
Michael Vahey / Raytheon
Lloyd Lewins / Raytheon
Drew Davidoff / Raytheon
Gillian Groves / Raytheon
Kenneth Prager / Raytheon
Charles Channell / Raytheon
Matt Kramer / Raytheon
John Granacki / University of Southern California–ISI
Jeff Draper / University of Southern California–ISI
Jeff LaCoss / University of Southern California–ISI
Craig Steele / Exogi
Jim Kulp / Mercury Computer Systems, Inc.
Abstract Presentation

Probabilistic CMOS Technology for Cognitive Information Processing

Krishna Palem / Georgia Institute of Technology
Bilge Akgul / Georgia Institute of Technology
Lakshmi Chakrapani / Georgia Institute of Technology
Abstract Presentation

Exploiting Reconfigurability for Text Search
Roger Chamberlain / Exegy & Washington Universlity
Mark Franklin / Exegy & Washington Universlity
Ronald Indeck / Exegy & Washington University
Abstract Presentation

VFORCE: VSIPL++ for Reconfigurable Computing Environments
Miriam Leeser / Northeastern University
Albert Conti / Northeastern University Nicholas Moore / Northeastern University
Laurie Smith King / College of the Holy Cross
Abstract Presentation
  Poster Précis A: Advanced Algorithms and Hardware
Rich Linderman / AFRL
  * Denotes presenter other than first listed author.
Poster A.1 Nonlinear Equalization of RF Receivers
Benjamin Miller / MIT Lincoln Laboratory
Brandon Kam / MIT Lincoln Laboratory
Joel Goodman / MIT Lincoln Laboratory
Gil Raz / GMR Research and Technology, Inc.
Abstract Précis Poster
Poster A.2 Parallelizing Exact Inference in Bayesian Networks
Viktor Prasanna / USC
Vasanth Krishna Namasivayam / USC
Animesh Pathak / USC
Abstract Précis
Poster A.3 Discrete Fourier Transform Compiler for FPGA and CPU/FPGA Partitioned Implementations
Markus Püschel / Carnegie Mellon University
* Paolo D’Alberto / Carnegie Mellon University
Peter Milder / Carnegie Mellon University
Franz Franchetti / Carnegie Mellon University
James Hoe / Carnegie Mellon University
José Moura / Carnegie Mellon University
Abstract Précis Poster
Poster A.4 Benchmark Results for Ultra-High Performance Scalable Processing Architecture for Embedded Defense Signal and Image Processing Applications
Stewart Reddaway / WorldScape
Nigel Bond / WorldScape
Rick Pancoast / Lockheed Martin
Justin Kidman / WorldScape
* Pete Rogina / WorldScape
Abstract Précis
Poster A.5 Petascale Computing in a Cubic Meter by 2015
James C. Anderson / MIT Lincoln Laboratory
Abstract Précis
  Posters on View at Burlington Marriott
Poster A.6
(Marriott)
Taking the HPEC Challenge with VSIPL++
Jules Bergmann / CodeSourcery
Don McCoy / CodeSourcery
Stefan Seefeld / CodeSourcery
Mark Mitchell / CodeSourcery
Abstract Précis
Poster A.7
(Marriott)
HPCS Sensor Processing and Knowledge Formation Benchmark Reference Implementation
Brian Sroka / The MITRE Corporation
Poster A.8
(Marriott)
Runtime Verification of Cognitive Applications
Jonathan Springer / Reservoir Laboratories
Donald Nguyen / Reservoir Laboratories
* Richard Lethin / Reservoir Laboratories
Abstract Précis Poster
Poster A.9
(Marriott)
Implementations of FIR for MONARCH Processor
Jinwoo Suh / University of Southern California–Information Sciences Institute
Janice McMahon / University of Southern California–Information Sciences Institute
Abstract Précis
  Session 2: Applications on New Architectures
Jeremy Kepner / MIT Lincoln Laboratory
Focus 2: Intelligent Software Technologies
Robert Bond / MIT Lincoln Laboratory
  * Denotes presenter other than first listed author.
  Successive Rank-Revealing Cholesky Factorizations on GPUs
Xiaobai Sun / Duke University
* Ty Fridrich / Duke University
Nikos Pitsianis / Duke University
Abstract Presentation
SAT Solvers for Investigation of Architectures for Cognitive Information Processing
Rich Lethin / Reservoir Laboratories
James Ezick / Reservoir Laboratories
Samuel Luckenbill / Reservoir Laboratories
Donald Nguyen / Reservoir Laboratories
Peter Szilagyi / Reservoir Laboratories
Abstract Presentation
  Field Programmable Multi-Cores: A New Class of Semiconductors
Gail Walters / CPU Technologies
Edward King / CPU Technologies
Abstract Presentation
Automatic Mapping of the HPEC Challenge Benchmarks
Nadya Bliss / MIT Lincoln Laboratory
Jason Dahlstrom / MIT Lincoln Laboratory
Daniel Jennings / MIT Lincoln Laboratory
Sanjeev Mohindra / MIT Lincoln Laboratory
Abstract Presentation
  Using VSIPL as an Embedded DoD Application Programming Interface (API) on DARPA Polymorphous Computing Architectures (PCA)
Kristin Daly / Lockheed Martin
Joseph Cook / Lockheed Martin
Rick Pancoast / Lockheed Martin
* Steve Crago / University of Southern California–ISI
Matthew French / University of Southern California–ISI
Karandeep Singh / University of Southern California–ISI
Jinwoo Suh / University of Southern California–ISI
Abstract Presentation
Program Analysis Tools for Application Specific Architectures
Maya Gokhale / Los Alamos National Laboratory
Matt Sottile / Los Alamos National Laboratory
Abstract Presentation
  The Past, Present, and Future of High Performance Embedded Computing (HPEC) in Reconnaissance Applications
James Broesch / General Atomics
 
  Advanced VLSI for Sensor Array Signal Processing
William Song / MIT Lincoln Laboratory
 
  2005 Awards
Jeremy Kepner / MIT Lincoln Laboratory
 
  Robots for Unstructured Environments: Now and on the Other Side of Exponentials
Rodney Brooks / MIT CSAIL
Biography
 
20 September
  Announcements
Robert Bond / MIT Lincoln Laboratory
 
  Keynote Address – HPEC: Looking Back and Projecting Forward
David Martinez / MIT Lincoln Laboratory
Biography Keynote Address
 
  Session 3: Challenging Computing Environments
Rick Pancoast / Lockheed Martin
Focus 3: High Performance Systems
David Cousins / BBN
  HPEC Progress and Opportunities: A DARPA Perspective
Charles Holland / DARPA/IPTO
Real-Time Adaptive Signal Processing Development for US Navy Torpedoes
Matthew Alexander / MIT Lincoln Laboratory
James C. Anderson / MIT Lincoln Laboratory
Nigel Lee / MIT Lincoln Laboratory
Francine Rayson / MIT Lincoln Laboratory
William Payne / MIT Lincoln Laboratory
Abstract Presentation
  Leveraging Carbon Nanotubes to Develop a Fourth-Generation Radiation Hardened Microprocessor for Space
Rick Ridgley / NRO
Abstract Presentation
Impact of CMP Design on High-Performance Embedded Computing
Patrick Crowley / Washington University
Mark Franklin / Washington University
Jeremy Buhler / Washington University
Roger Chamberlain / Washington University
Abstract Presentation
  Single Integrated Air Picture (SIAP)
Col Stephen “Scotty” Fairbairn / SIAP
Presentation
Filesystems for Streaming Databases
Bradley Kuszmaul / MIT CSAIL
Abstract Presentation
  Dependable Multiprocessing (DM)
John Samson, Jr. / Honeywell
Gary Gardner / Honeywell
David Lupia / Honeywell
Alan George / University of Florida
Minesh Patel / Tandel Systems, Inc.
Paul Davis / Tandel Systems, Inc.
Vikas Aggarwal / Tandel Systems, Inc.
Zbigniew Kalbarczyk / University of Illinois
Raphael Some / Jet Propulsion Laboratory
Abstract Presentation
 
  Poster Précis B: High Performance FPGA Technologies and Applications
Rick Pancoast / Lockheed Martin
  * Denotes presenter other than first listed author.
Poster B.1 Experimental Analysis of Multi-FPGA Architectures over RapidIO for Space-Based Radar Processing
Chris Conger / University of Florida
David Bueno / University of Florida
Alan George / University of Florida
Abstract Précis Poster
Poster B.2 Radar Digital Beam-Former Utilizing FPGA Based COTS Processors
John Fontana / Lockheed Martin
Edward Monastra / Lockheed Martin
Abstract Précis
Poster B.3 An FPGA-Based Dynamic Load-Balancing Processor Architecture for Solving N-body Problems
Jonathan Phillips / Utah State University
Matthew Areno / Utah State University
Brandon Eames / Utah State University
Aravind Dasu / Utah State University
Abstract Précis Poster
Poster B.4 Hybrid Floating Point Technique Yields 1.2 Gigasample per Second 32 to 2048 point Floating Point FFT in a Single FPGA
Raymond Andraka / Andraka Consulting Group
Abstract Précis Poster
Poster B.5 FPGA Technology Meets the Multicomputer Environment – Improving Processing Performance and Bandwidth in Advanced Naval Radar Missions
Sarah Leeper / Mercury Computer Systems, Inc.
Mike laquinto / Lockheed Martin
Richard Brooks / Mercury Computer Systems, Inc.
Joseph Finnivan / Mercury Computer Systems, Inc.
Abstract Préics
Poster B.6 Design of Path Optimization Algorithm Using COTS Field Programmable Gate Array Hardware and Software Platforms
Neil Harold / Nallatech
John Ostapovich / Nallatech
Rick Pancoast / Lockheed Martin
Jon Russo / Lockheed Martin
Abstract Précis
Poster B.7 Multi-FPGA Based High Performance LU Decomposition
Arvind Sudarsanam / Utah State University
Seth Young / Utah State University
Thomas Hauser / Utah State University
* Aravind Dasu / Utah State University
Abstract Précis
Poster B.8 Improving the Performance of Parallel Backprojection on a Reconfigurable Supercomputer
Benjamin Cordes / Northeastern University
Miriam Leeser / Northeastern University
Eric Miller / Northeastern University
Richard Linderman / AFRL
Abstract Précis
Poster B.9 A New Class of High Performance FFTs
Greg Nash / Centar
Abstract Précis Poster
Poster B.10 Running Simulink-Based Designs on SRC-6
David Meixner / National Center for Supercomputing Applications at Univ. of Illinois–Urbana-Champaign
Volodymyr Kindratenko / National Center for Supercomputing Applications at Univ. of Illinois–Urbana-Champaign
David Pointer / National Center for Supercomputing Applications at Univ. of Illinois–Urbana-Champaign
Abstract Précis
Poster B.11 High Performance Low Density Parity Check and Turbo Decoding FPGA Implementation
Ryan Shoup / MIT Lincoln Laboratory
Abstract Précis
Poster B.12 Close-to-Concept Coding for Configurable Computing
Henk Spaanenburg / Advanced Principles Group
Joe Thompson / Advanced Principles Group
Abstract Précis
  Session 4: Cognitive Computing
William Harrod / DARPA / IPTO
Focus 4: High Performance Rapid Prototyping
Albert Reuther / MIT Lincoln Laboratory
  CEARCH: Cognition Enabled Architecture
Stephen Crago / University of Southern California–ISI
Janice McMahon / University of Southern California–ISI
Abstract Presentation
HPEC Challenge SAR Benchmark pMatlab Implementation and Performance
Julia Mullen / MIT Lincoln Laboratory
Theresa Meuse / MIT Lincoln Laboratory
Jeremy Kepner / MIT Lincoln Laboratory
Abstract Presentation
  R-Stream: A Parametric High Level Compiler
Eric Schweitz / Reservoir Laboratories
Rich Lethin / Reservoir Laboratories
Allen Leung / Reservoir Laboratories
Benoit Meister / Reservoir Laboratories
Abstract Presentation
Applying Advanced Computing to Improve High-Fidelity Radar Data Simulations
Christopher Hulbert / Information Systems Laboratory
Jameson Bergin / Information Systems Laboratory
Paul Techau / Information Systems Laboratory
Abstract Presentation
  COGENT: An Innovative Architecture for Cognitive Processing
Julius Bogdanowicz / Raytheon
John Granacki / University of Southern California–ISI
Abstract Presentation
Interactive Supercomputing’s Star-P Platform: Parallel MATLAB and MPI Homework Classroom Study on High Level Language Productivity
Alan Edelman / MIT & Interactive Supercomputing
Parry Husbands / Interactive Supercomputing & Lawrence Berkeley National Laboratory
Steve Leibman / Interactive Supercomputing
Abstract Presentation
  Panel: Looking Forward, Looking Back
Moderator:
James C. Anderson / MIT Lincoln Laboratory
Presentation
 
 

Distinguished Panelists:
Jerry Oesterheld / SimVentions, Inc.
Stephen Poole / Los Alamos National Laboratory
Presentation
Richard Ridgley / National Reconnaissance Office
Gary Shaw / MIT Lincoln Laboratory

 
21 September
  Session 5: Standards and Metrics
Craig Lund / Mercury Computer Systems
Focus 5: Harnessing the Cell Processor
Sharon Sacco / MIT Lincoln Laboratory
  * Denotes presenter other than first listed author.
  HPC Challenge
Jeremy Kepner / MIT Lincoln Laboratory
Presentation
Performance Benchmarks and Programmability of the IBM/Sony/Toshiba Cell Broadband Engine Processor
Luke Cico / Mercury Computer Systems, Inc.
Robert Cooper / Mercury Computer Systems, Inc.
Jon Greene / Mercury Computer Systems, Inc.
Michael Pepe / Mercury Computer Systems, Inc.
Abstract Presentation
  Performance Complexity: A New Execution Time Metric
Erich Strohmaier / Lawrence Berkeley National Laboratory
Presentation
Leveraging Multicomputer Frameworks for Use in Multi-Core Processors
Yael Steinsaltz / Mercury Computer Systems, Inc.
Scott Geaghan / Mercury Computer Systems, Inc.
Myra Jean Prelle / Mercury Computer Systems, Inc.
Brian Bouzas / Mercury Computer Systems, Inc.
Abstract Presentation
  Keynote Address – Internet Evolution and Governance: Background, Lessons Learned, and Future Directions
Robert Kahn / Corporation for National Research Initiatives
Biography

Speech Recognition on Cell Broadband Engine
Holger Jones / Lawrence Livermore National Laboratory
Michael Perrone / IBM Watson Research Center
* Yang Liu / Lawrence Livermore National Laboratory
Abstract Presentation

  The HPEC Challenge Benchmark Suite
Ryan Haney / MIT Lincoln Laboratory
Theresa Meuse / MIT Lincoln Laboratory
Jeremy Kepner / MIT Lincoln Laboratory
Abstract Presentation
 
  Data Reorganization Interface (DRI): Past Perspective, Future Vision, New Results, and Increased Availability
Kenneth Cain, Jr. / Mercury Computer Systems, Inc.
Abstract Presentation
 
  Poster Précis C: Software Standards
Craig Lund / Mercury Computer Systems
Poster C.1 Computational Requirements of a Non-combinatorial Detection of Multiple Targets in High GMTI Clutter
Simon Streltsov / LongShortWay, Inc.
Ilya Muchnik / LongShortWay, Inc.
Sergey Petrov / LongShortWay, Inc.
Leonid Perlovsky / AFRL
Ross Deming / Anteon Corporation
Abstract Précis
Poster C.2 Extending the VSIPL Standard to Other Precisions: Gaining the Full Performance of Current Processors
Albert Garrett / Verari Systems
Anthony Skjellum / Verari Systems
Abstract Précis
Poster C.3 A Comparison of VSIPL++ Performance to VSIPL and Mercury SAL
Thomas Steck / Lockheed Martin
Abstract Précis
Poster C.4 Reusing Verification Components in System-Level Modeling Environments
Ambar Sarkar / Paradigm Works
Jim Crocker / Paradigm Works
Bob Ionta / The MathWorks, Inc.
Abstract Précis
Poster C.5 Abstract Machines for RASCs and Signal/Image Processing
Lenore Mullin / College of Computing and Information at SUNY–Albany
James Raynolds / College of Nanoscale Science and Engineering at SUNY–Albany
Ian Grout / University of Limerick
Qiang Li / College of Computing and Information at SUNY–Albany
Jeffrey Ryan / University of Limerick
Abstract Précis
Poster C.6 The Measure Polytope: Low Latency and High Bandwidth on Commodity Interconnects
Kurt Keville / MIT
Dan Vickery / MIT
Abstract Précis
Poster C.7 DIFdoc: A Standard Format for Visualizing Hierarchical Dataflow Representations
Ivan Corretjer / University of Maryland
Shuvra Bhattacharyya / University of Maryland
Abstract Précis
Poster C.8 The Impact of Programming Difficulty on Hardware Obsolescence
James Steed / Gedae
William Lundgren / Gedae
Kerry Barnes / Gedae
Abstract Précis
Poster C.9 X-Sim: A Federated Heterogeneous Simulation Environment
Roger Chamberlain / Washington University
Saurabh Gayen / Washington University
Eric Tyson / Washington University
Mark Franklin / Washington University
Patrick Crowley / Washington University
Abstract Précis
Poster C.10 System Overhead Management with Virtual Power Centers for Biometric Applications
Kevin Howard / Massively Parallel Technologies
James Lupo / Massively Parallel Technologies
Abstract Précis
Poster C.11 Modeling Concurrency in NOC for Embedded Systems
Ankur Agarwal / Florida Atlantic University
Ravi Shankar / Florida Atlantic University
Abstract Précis
Poster C.12 Algorithm Development for Future High Performance Systems Jigsaw: An Early Case Study
Imran Khan / SoftServ International
Abstract Précis
Poster C.13 Software Decomposition for Multicore Architectures
Ankit Jain / Florida Atlantic University
Ravi Shankar / Florida Atlantic University
Abstract Précis
  Session 6: Awards Session
Jeremy Kepner / MIT Lincoln Laboratory
 
  VSIPL++ Acceleration Using Commodity Graphics Processors
Daniel Campbell / Georgia Institute of Technology
Abstract Presentation
 
  Enabling Cognitive Architectures for UAV Mission Planning
Jon Russo / Lockheed Martin
Mohammed Amduka / Lockheed Martin
Keith Pedersen / Lockheed Martin
Richard Lethin / Reservoir Laboratories
Jonathan Springer / Reservoir Laboratories
Rajit Manohar / Cornell University
Rami Melhem / University of Pittsburgh
Abstract Presentation
 
  Spaceborne Processor Array in Multifunctional Structure (SPAMS) Edward Chow / Jet Propulsion Laboratory
Don Schatzel / Jet Propulsion Laboratory
Bill Whitaker / Jet Propulsion Laboratory
Thomas Sterling / Louisiana State University
Abstract Presentation
 
  Exploring the Cell with HPEC Challenge Benchmarks
Sharon Sacco / MIT Lincoln Laboratory Glenn Schrader / MIT Lincoln Laboratory Jeremy Kepner / MIT Lincoln Laboratory
Abstract Presentation
 
  Adjourn / Awards
Jeremy Kepner / MIT Lincoln Laboratory