20 September

Check-In / Poster Setup / Continental Breakfast

Welcome
David Martinez / MIT Lincoln Laboratory

Keynote Address
Brig Gen Gary Connor / Hanscom Air Force Base

0905

Opening Remarks
Robert Bond / MIT Lincoln Laboratory

Session 1:  Advanced Hardware
Robert Bond / MIT Lincoln Laboratory

Future of Embedded Software from an Historical Perspective (Invited)
Robert Graybill / DARPA IPTO

Cell Processor (Invited)
James Kahle / IBM

1025

Break

1040

Applications Kernels on Graphics Processing Units: An Analysis of Hidden Markov Models, Support Vector Machines, Hyperspectral Imaging, and Latent Semantic Indexing
Sean Ahern / Lawrence Livermore National Laboratory
David Bremer / Lawrence Livermore National Laboratory
John R. Johnson / Lawrence Livermore National Laboratory
Holger Jones / Lawrence Livermore National Laboratory
Yang Liu / Lawrence Livermore National Laboratory
Jeremy Meredith / Lawrence Livermore National Laboratory
Sheila Vaidya / Lawrence Livermore National Laboratory
Candace Culhane/ Department of Defense

1110

Embedding Applications within a Storage Appliance
Roger Chamberlain / Washington University

Poster / Demo A:  FPGAs Everywhere
Michael Vai / MIT Lincoln Laboratory

1150

Poster / Demo A PrÈcis

Poster A.1

Super-FPGA:  Overcoming Von Neumann to Save Moore
Venkatesh Akella / University of California
Soheil Ghiasi / University of California

Mapping of a 2D SAR Backprojection Algorithm to an SRC Reconfigurable Computing MAP Processor
Peter Buxa / AFRL, Sensors Directorate
LeRoy Gorham / AFRL, Sensors Directorate
Mathew Lukacs / AFRL, Sensors Directorate
David Caliga / SRC Computers, Inc.

Poster A.3

Enhancing FPGA-Based Encryption on the Cray XD1
Joseph Fernando / Ohio Supercomputer Center-Springfield
Dennis Dalessandro / Ohio Supercomputer Center-Springfield
Ananth Devulapalli / Ohio Supercomputer Center-Springfield
Ashok Krishnamurthy / Ohio Supercomputer Center-Springfield

A Superpipelined CORDIC Unit
Michael Fitzharris / Drexel University
Jeremy Johnson / Drexel University
Prawaat Nagvajara / Drexel University
Servesh Tiwari / Drexel University

Real-Time FPGA Implementation of Adaptive Beamforming Using QR Decomposition
Michael Gay / QinetiQ, Ltd.

A Data-Driven SoC System for Embedded Continuous Speech Recognition
Raymond Hoare / University of Pittsburgh
Kshitij Gupta / University of Pittsburgh
Jeffery Schuster / University of Pittsburgh

Iterative Demodulation and Turbo Decoding for Distributed Radio Receivers
Preston Jackson / MIT Lincoln Laboratory
Joel Goodman / MIT Lincoln Laboratory
Hector Chan / MIT Lincoln Laboratory

Automatic Mapping of the MATLAB Code to Parallel FPGA's on the SGI Altix
Michael Murphy / Silicon Graphics, Inc.
Michael Raymond / Silicon Graphics, Inc.
Steve Reinhardt / Silicon Graphics, Inc.

Poster A.9

Interface Techniques for Microprocessors Embedded Within FPGA's
Joshua Noseworthy / Northeastern University
Miriam Leeser / Northeastern University

Poster A.10

Parallel FFT and Parallel Cyclic Convolution Algorithms with Regular Structure and No Processor Intercommunication
Marvi Teixeira / Polytechnic University of Puerto Rico
Miguel De Jesus / Polytechnic University of Puerto Rico
Yamil Rodriguez / Polytechnic University of Puerto Rico

A Methodology for Exploring Finite-Precision Effects when Solving Linear Systems of Equations with Least-Squares Techniques in Fixed-Point Hardware
Ramon Uribe / AccelChip, Inc.
Thomas Cesear / AccelChip, Inc.

Poster A.12

Rapid Prototyping of a Real-Time Range Compression Processor
Michael Vai / MIT Lincoln Laboratory
Thomas Anderson / MIT Lincoln Laboratory
Albert Horst / MIT Lincoln Laboratory
Robert Gallagher / MIT Lincoln Laboratory
Larry Retherford / MIT Lincoln Laboratory
Tom Emberley / MIT Lincoln Laboratory
Preston Jackson / MIT Lincoln Laboratory
Cy Chan / MIT Lincoln Laboratory
Charles Rader / MIT Lincoln Laboratory
Huy Nguyen / MIT Lincoln Laboratory
Paul Monticciolo / MIT Lincoln Laboratory

Lunch / View Posters

AUDITORIUM

Room S2-180

1345

Session 2:  Hardware Architecture and System Metrics
Paul Monticciolo / MIT Lincoln Laboratory

Focus 1:  Algorithms and FPGAs
Henk Spaanenburg / Advanced Principles Group, Inc.

A Next Generation Ultra-High Performance Scalable Processing Architecture for Embedded Defense Signal and Image Processing Applications
Stewart Reddaway / WorldScape Defense, LLC
Rick Pancoast / Lockheed Martin, MS2
Dhon Paulo / Lockheed Martin, MS2
Pete Rogina / WorldScape Defense, LLC

Unbounded Transactional Memory (Invited)
Charles E. Leiserson / MIT

A VLIW Processor with Hardware Functions:  Increasing Performance While Reducing Power
Raymond Hoare / University of Pittsburgh
Alex Jones / University of Pittsburg
Dara Kusic / University of Pittsburg
Joshua Fazekas / University of Pittsburg
Gayatri Mehta / University of Pittsburg
John Foster / University of Pittsburg
 

High-Performance FPGA-Based QR Decomposition
Huy Nguyen / MIT Lincoln Laboratory
James Haupt / MIT Lincoln Laboratory
Michael Eskowitz / MIT Lincoln Laboratory
Birol Bekirov / MIT Lincoln Laboratory
Jonathan Scalera / MIT Lincoln Laboratory
Thomas Anderson / MIT Lincoln Laboratory
Michael Vai / MIT Lincoln Laboratory
Kenneth Teitelbaum / MIT Lincoln Laboratory

Implementations of Signal Processing Kernels Using Stream Virtual Machine for Raw Processor
Jinwoo Shu / University of Southern California, ISI
Stephen Crago / University of Southern California, ISI
Dong-In Kang / University of Southern California, ISI
Janice McMahon / University of Southern California, ISI

Pipelined Data Path for an IEEE-754 64-Bit Floating-Point Jacobi Solver
Gerald Morris/ University of Southern California
Viktor Prasanna / University of Southern California

1525

Break / View Posters

Break / View Posters

1550

The HPEC Challenge Benchmark Suite
Ryan Haney / MIT Lincoln Laboratory
Theresa Meuse / MIT Lincoln Laboratory
Jeremy Kepner / MIT Lincoln Laboratory
James Lebak / MIT Lincoln Laboratory

Sparse Matrix-Vector Multiplication Kernel on a Reconfigurable Computer
Sreesa Akella / University of South Carolina
Melissa Smith / Oak Ridge National Laboratory
Richard Mills / Oak Ridge National Laboratory
Sadaf Alam / Oak Ridge National Laboratory
Richard Barrett / Oak Ridge National Laboratory
Jeffrey Vetter / Oak Ridge National Laboratory

1620

A Relative Development Time Productivity Metric for HPC Systems
Andrew Funk / MIT Lincoln Laboratory
Jeremy Kepner / MIT Lincoln Laboratory
Victor Basili / University of Maryland
Lorin Hochstein / University of Maryland

GPGP:  General Purpose Computation Using Graphics Processors
Naga Govindaraju / University of North Carolina at Chapel Hill
Ming Lin / University of North Carolina at Chapel Hill
Dinesh Manocha / University of North Carolina at Chapel Hill

1650

Mitigating the Risks of High Performance Computational Science and Engineering (Invited)
Douglas Post / HPCMO

1720

Adjourn

1800

Reception (Burlington Marriott)

1845

Banquet Presentation
The Software Industry:  How Business Models Are Changing from Products to Services
Michael Cusumano / MIT Sloan

1930

Banquet

21 September

0730

Check-In / Continental Breakfast

0830

Announcements
Robert Bond / MIT Lincoln Laboratory

0835

Session 3:  Advanced Parallel Environments
Mike Harris / BAE Systems

0845

X10 Programming (Invited)
Vivek Sarkar / IBM Research

0915

MathWorks Recent and Future Solutions for High Productivity (Invited)
Roy Lurie / The MathWorks
Cleve Moler / The MathWorks

0945

Break

1000

Advanced Hardware and Software Technologies for Ultra-long FFT's
Hahn Kim / MIT Lincoln Laboratory
Jeremy Kepner / MIT Lincoln Laboratory
Michael Vai / MIT Lincoln Laboratory
Crystal Khan / MIT Lincoln Laboratory

1030

An Interactive Approach to Parallel Combinatorial Algorithms with Star-P
John Gilbert / University of California, Santa Barbara
Viral Shah / University of California, Santa Barbara
Todd Letsche / Silicon Graphics, Inc.
Steve Reinhardt / Silicon Graphics, Inc.
Alan Edelman / MIT

1100

Poster / Demo B:  High Performance Software Technologies
Albert Reuther / MIT Lincoln Laboratory

1110

Poster/Demo B PrÈcis

Poster B.1

Process and Shared Object Library Scheduling for High-Performance Hybrid-Reconfigurable Embedded Systems
Philip Brisk / UCLA Computer Science Department
Adam Kaplan / UCLA Computer Science Department
Majid Sarrafzadeh / UCLA Computer Science Department

Poster B.2

Improving Rapid Application Development Environments Through Coordination
Nicholas Carriero / Yale University
David Gelernter / Yale University
Martin Schultz / Yale University

Poster B.3

Performance Estimates of a STAP Benchmark on the IBM Cell Processor
Luke Cico / Mercury Computer Systems
Jon Greene / Mercury Computer Systems
Robert Cooper / Mercury Computer systems

Poster B.4

Open HPEC Systems:  Design and Profiling Tools for Multiprocessor Signal Processing Applications using MPI
BenoÓt Guillon / Thales Computers
JÈrÙme Blanc / Thales Computers
BenoÓt Masson / Thales Computers
Gerard Cristau / Thales Computers
Vincent Chuffart / Thales Computers

Poster B.5

Integration of Interactive MATLABÆ and Linux Clusters
Joan Puig Giner / Interactive Supercomputing, Inc.
Vern Shrauger / Interactive Supercomputing, Inc.

Poster B.6

Application of Functional Coverage-Driven-Verification (CDV) Methodology to Real-Time Embedded Systems-on-Chip (SoC) for HW/SW State-Space Co-verification and Architectural Exploration
Giles Hall / Cadence Design Systems, Inc.
J. Marc Edwards / Cadence Design Systems, Inc.

Poster B.7

Combining Moore's Law and Amdahl's Law Showing How Software Can Save Moore's Price/Performance Model
Kevin Howard / Massively Parallel Technologies
James Lupo / Massively Parallel Technologies

Poster B.8

What Makes HPEC Applications Challenging? - Understanding Application/Architecture Interactions
David Koester / The MITRE Corporation

Poster B.9

InfiniPath:  A New High Speed, Low Latency Cluster Interconnect
Greg Lindahl / PathScale, Inc.

Poster B.10

How Code Generation Will Save Moore's Law
William Lundgren / Gedae, Inc.
Kerry Barnes / Gedae, Inc.
James Steed / Gedae, Inc.

Poster B.11

Evaluation of Graphical Programming and Automated Code Generation Software Tools for Use in Missile Defense Applications
Rick Pancoast / Lockheed Martin Corporation, MS2
Chris Robbins / Management Communications and Control, Inc.
Rocco Dragone / Lockheed Martin Corporation, MS2
Joann Harvey / Lockheed Martin Corporation, MS2
Walter Spehalski / Lockheed Martin Corporation, MS2

Poster B.12

FPGA Implementation of MIMO Wireless Receiver in Interference
Tri Phuong / MIT Lincoln Laboratory
Derek Young / MIT Lincoln Laboratory
Daniel Bliss / MIT Lincoln Laboratory
Keith Forsythe / MIT Lincoln Laboratory

Poster B.13

Applying Model Driven Architecture to Radar Systems
Terri Potts / Raytheon Company
Stefanie Chiou / Raytheon Company
Gregory Eakman / PathFinder Solutions

Poster B.14

Scalable and Portable Supercomputing
Gail Walters / CPU Technology, Inc.
Scott Nelson / CPU Technology, Inc.
Steven Manuel / CPU Technology, Inc.

Poster B.15

Accelerating Blocked Matrix-Matrix Multiplication Using a Software-Managed Memory Hierarchy with DMA
Roland Wunderlich / Carnegie Mellon University
Markus P¸schel / Carnegie Mellon University
James Hoe / Carnegie Mellon University

1205

Lunch / View Posters

1335

Session 4:  Award Finalist Session - Advanced Software
Rick Pancoast / Lockheed Martin

1345

pMapper:  Automatic Mapping of Parallel Matlab Programs
Nadya Travinin / MIT Lincoln Laboratory
Henry Hoffman / MIT Lincoln Laboratory
Robert Bond / MIT Lincoln Laboratory
Hector Chan / MIT Lincoln Laboratory
Jeremy Kepner / MIT Lincoln Laboratory
Edmund Wong / MIT Lincoln Laboratory

1415

VSIPL++Pro - A High-Performance VSIPL++ Implementation
Jules Bergmann / CodeSourcery, LLC
Mark Mitchell / CodeSourcery, LLC
Stefan Seefeld / CodeSourcery, LLC
Zack Weinberg / CodeSourcery, LLC
Nathan Myers / CodeSourcery, LLC
Rick Pancoast / Lockheed Martin, NE&SS

1445

High-Productivity Stream Programming for High-Performance Systems
Rodric Rabbah / MIT CSAIL
Bill Thies / MIT CSAIL
Michael Gordon / MIT CSAIL
Janis Sermulins / MIT CSAIL
Saman Amarasinghe / MIT CSAIL

1515

Break

1540

Panel:  "Will Software Save Moore's Law?"
Moderator: James Anderson / MIT Lincoln Laboratory
Distinguished Panelists:
William Bail/The MITRE Corporation
Robert Bond / MIT Lincoln Laboratory
Vivek Sarker / IBM Research
Guy Steele / Sun Mircosystems

1730

Adjourn

22 September

0730

Check-In / Continental Breakfast

0830

Announcements
Robert Bond / MIT Lincoln Laboratory

0835

Software Producibility (Invited)
John Grosh / OSD

0905

Session 5:  Standards Usage and Update
Craig Lund / Mercury Computer Systems

Using the OCP Standard for FPGA Reuse
Ian Mackintosh / OCPIP

OMG Data-Distribution Service (DDS):  Architectural Update
Joseph Schlesselman / Real-Time Innovations, Inc.
Gerardo Pardo-Castellote / Real-Time Innovations, Inc.,
Bert Farabaugh / Real-Time Innovations, Inc.

0955

Eclipse Tools
Brian Selic / IBM Rational Software

1010

Break

1025                      

UML2.0 Profiles for Modeling Real-Time and Quality of Service
Sky Matthews / IBM Rational Software

1040

Integrating VSIPL Support in the Dataflow Interchange Format
Chia-Jui Hsu / University of Maryland at College Park
Shuvra Bhattacharyya / University of Maryland at College Park

1055

Implementation of an Embedded DoD VSIPL Application on the DARPA Polymorphous Computing Architectures (PCA) RAW Processor
Joseph Cook / Lockheed Martin, MS2
Stephen Crago / University of Southern California, ISI
Lou Morda / Lockheed Martin, MS2
Rick Pancoast / Lockheed Martin, MS2
Jinwoo Shu / University of Southern California, ISI

1115

Poster / Demo C:  Software Standards
Jeremy Kepner / MIT Lincoln Laboratory

1125

Poster/Demo C PrÈcis

Poster C.1

VSIPL ++:  A Single Processing Library Scaling with Moore's Law
Jules Bergmann / CodeSourcery, LLC
Jeffrey Oldham / CodeSourcery, LLC

Poster C.2

A Software Methodology for Real-Time Target Recognition
Wim Bohm / Colorado State University
Steve Heistand / SRC Computers, Inc.
David Caliga / SRC Computers, Inc.
Jeff Hammes / SRC Computers, Inc.

Poster C.3

An FPGA API for VSIPL ++
Ben Cordes / Northeastern University
Miriam Leeser / Northeastern University
Joe Tarkoff / Northeastern University

Poster C.4

Implementation of Floating-Point VSIPL Functions on FPGA-Based Reconfigurable Computers Using High-Level Languages
Malachy Devlin / Nallatech, Ltd.
Robin Bruce / Institute of System-Level Integration
Stephen Marshall / Strathclyde University

Poster C.5

Evaluation of an Embedded Signal Processing System for Generic Air Traffic Processor
Robert Hamilton / CSP, Inc.
Stephen Shank / Lockheed Martin Corporation
John Johansson / Lockheed Martin Corporation
Henry Chin / Lockheed Martin Corporation
Rick Pancoast / Lockheed Martin Corporation
Leon Trevito / Lockheed Martin Corporation
Peter Case / Lockheed Martin Corporation
Aubrey Chan / Lockheed Martin Corporation
Juan Antonio Villalba Camacho / Indra
Francisco Alvarez Solvez / Indra
Eva Valentin Ramiro / Indra

Poster C.6

Return of the Hypercube:  10 Gbps per Node over 802.3av, Scaling LInearly to 12 Nodese
Kurt Keville / MIT
Robert Tompkins / Clarkson University

Poster C.7

FGPA-Based Signal Acquisition System
Sarah Leeper / Mercury Computer Systems, Inc.
Robert Frisch / Mercury Computer Systems, Inc..
Scott Geaghan / Mercury Computer Systems, Inc.
Scott Tetreault / Mercury Computer Systems, Inc.
Michael Vinskus / Mercury Computer Systems, Inc.
Erich Whitney / Mercury Computer Systems, Inc.

Poster C.8

The Scalable Software Interconnect for Distributed Radar Signal Processing
Jeff Rudin / Mercury Computer Systems, Inc.
Luke Cico / Mercury Computer Systems, Inc.
Ken Cain / Mercury Computer Systems, Inc.
Myra Jean Prelle / Mercury Computer Systems, Inc.
Ethan Luce / Raytheon Company
Terri Potts / Raytheon Company

Poster C.9

A CMOS Digital Decoder ASIC for an Advanced Digital Receiver
Charles Snell / Lockheed Martin MS2
Leopold Pellon / Lockheed Martin MS2
Junius Pridgen / Lockheed Martin MS2
Melody Jiang / Lockheed Martin MS2
Dipakkumar Tailor / Lockheed Martin MS2
David Lusk / Lockheed Martin MS2

1200

Lunch

1300

Session 6:  Advanced Systems
William Harrod / SGI
Auditorium

Focus 2:  Hardware Tools and Network Technologies
Steve Paavola / Analogic
Room S2-180

1330

Adapting Parallel Backprojection to an FPGA Enhanced Distributed Computing Environment
Albert Conti / Northeastern University
Ben Cordes / Northeastern University
Miriam Leeser / Northeastern University
Eric Miller / Northeastern University
Richard Linderman / AFRL/IF

C-Based Hardware Design Platform for a Dynamically Reconfigurable Processor
Phil Mulholland / IPFlex, Inc.
Keisuke Ide / IPFlex, Inc.
Tomoyoshi Sato / IPFlex, Inc.

1400

An Embedded DoD Discrimination and Classification Processing Challenge for DARPA Architectures for Cognitive Information Processing (ACIP)
Steve Crago / University of Southern California
Rocco Dragone / Lockheed Martin MS2
Mike Iaquinto / Lockheed Martin  MS2
Jim Kilian / Lockheed Martin  MS2
Janice McMahon / University of Southern California
Rick Pancoast / Lockheed Martin  MS2

Application Development for Hybrid Pipelined Systems
Mark Franklin / Washington University in St. Louis
Patrick Crowley / Washington University in St. Louis
Roger Chamberlain / Washington University in St. Louis
Jeremy Buhler / Washington University in St. Louis
James Buckley / Washington University in St. Louis

1430

Break (View Posters)

Break (View Posters)

1450

RapidIO-Based Space System Architectures for Synthetic Aperture Radar and Ground Moving Target Indicator
David Bueno / HCS Research Laboratory, University of Florida
Chris Conger / HCS Research Laboratory, University of Florida
Adam Leko / HCS Research Laboratory, University of Florida
Ian Troxel / HCS Research Laboratory, University of Florida
Alan George / HCS Research Laboratory, University of Florida

A Streaming Virtual Machine for GUPs
Kenneth Mackenzie / Reservoir Labs, Inc.
Daniel Campbell / Reservoir Labs, Inc.
Peter Szilagyi / Reservoir Labs, Inc.

1520

Case Study:  Real-Time Demonstration of a Knowledge-Aided STAP Algorithm Using PVL
Martin Courtney / Information Systems Laboratories, Inc.
John Don Carlos / Information Systems Laboratories, Inc.
Jameson Bergin / Information Systems Laboratories, Inc.

An Integrated Photonic Network for Multi-Processor Applications
Assaf Shacham / Columbia University
Keren Bergman / Columbia University

1550

Performance Analysis of Kernel Benchmarks on Tiled Architectures
James Lebak / MIT Lincoln Laboratory
Ryan Haney / MIT Lincoln Laboratory
Matt Alexander / MIT Lincoln Laboratory
Hector Chan / MIT Lincoln Laboratory
Edmund Wong / MIT Lincoln Laboratory

A High Performance Programming Model for Large-Scale Molecular Dynamics Calculations on Reconfigurable Supercomputers
Luis Cordova / University of South Carolina
Melissa Smith / Oak Ridge National Laboratory
Sadaf Alam / Oak Ridge National Laboratory
Jeffrey Vetter / Oak Ridge National Laboratory

1620

High Performance, Environmentally Adaptive Fault Tolerant Computing (EAFTC)
John Samson Jr. / Honeywell, Inc.
Jeremy Ramos / Honeywell, Inc.
Alan George / University of Florida
Minesh Patel / Tandel Systems, LLC
Raphael Some / Jet Propulsion Laboratory

High Performance Computing from a General Formalism:  Conformal Computing© Techniques Illustrated with a Quantum Computing Example
Lenore Mullin / State University of New York - Albany
James Raynolds / State University of New York - Albany
R.M. Mattheyses/ GE Global Research

Adjourn / Awards
Jeremy Kepner / MIT Lincoln Laboratory