Introducing the HPEC Challenge Benchmark Suite
The embedded computing community is faced with an ever increasing challenge of producing software, firmware, and hardware to meet the demands of high performance commercial and DoD applications. These application requirements are driving the use of new computer processing elements with new processor architectures and increasing the complexity of application software.
To provide a means to quantitatively evaluate such high performance embedded computing (HPEC) systems, we propose a challenge to the community in the form of a suite of benchmarks. The HPEC Challenge benchmark suite consists of a set of single-processor kernel benchmarks and a multiprocessor application benchmark. The kernel benchmarks address important operations across a broad range of DoD signal and image processing applications. The application benchmark implements a scalable Synthetic Aperture Radar (SAR) application that is representative of one of the most common functions in DoD surveillance systems.
More information on the benchmarks is provided on the Benchmark page. Links to benchmark description pages can also be found below. The HPEC Challenge software distribution can be found on the Software page. Viewing or posting benchmark results to this web site requires registration to the site. Go to the Registration page to obtain a username and password.
The HPEC Challenge benchmarks and web site are works in progress. Please contact hpecChallenge@ll.mit.edu with any comments, questions, or suggestions for improvement.
- Time-Domain Finite Impulse Response Filter Bank - TDFIR
- Frequency-Domain Finite Impulse Response Filter Bank - FDFIR
- QR Factorization - QR
- Singular Value Decomposition - SVD
- Constant False-Alarm Rate Detection - CFAR
- Pattern Matching - PM
- Graph Optimization via Genetic Algorithm - GA
- Database Operations - DB
- Corner Turn Benchmark - CT