Lincoln Laboratory Microelectronics Facilities

Microelectronics LaboratorySilicon Device Fabrication.  Lincoln Laboratory fabricates silicon devices in the 70,000 square foot microelectronics fabrication facility pictured at the right. There are 8,100 ft2 of class-10 and 10,000 ft2 of class-100 clean-room areas.

The equipment set is continuously updated and includes a production-class complementary metal-oxide semiconductor (CMOS) toolset with angled ion-implantation, cluster metallization and dry etch equipment, chemical-mechanical planarization equipment, rapid thermal processing, and advanced lithography capabilities (i-Line, 248 nm, 193 nm). Currently, the wafer size is 150 mm.

In this facility, we have fabricated a number of different designs of multi-megapixel charge-coupled device (CCD) imagers (visible, UV, X-ray), most of which are thinned and back-illuminated.

Molecular-beam epitaxy system.Molecular-beam epitaxy system.

Using a molecular-beam epitaxy system (shown at the right), we have developed highly stable and highly sensitive back-illuminated passivation layers for devices operating in the UV, EUV, and soft X-ray bands. These imagers have been used in Department of Defense and scientific programs and in ground-based astronomy observatories and satellite programs, such as the NASA Chandra Observatory and the Extreme Ultraviolet Variability Experiment (EVE).

We have developed several families of CMOS devices [0.25 μm mixed-signal fully depleted silicon-on-insulator (FDSOI) CMOS, 0.18 μm low-power FDSOI CMOS], and we are currently developing sub-100 nm FDSOI CMOS. Using experience gained with FDSOI wafers, we have developed a 3D circuit-stacking technology.

Staff working in the fabrication facility.Staff working in the fabrication facility.

We also fabricate Geiger-mode single-photon-counting detectors in this facility. We have developed techniques to bond these devices and make through-array contacts to commercial CMOS readout circuits. These devices have been integrated into several field-operable flash LADAR systems.

Other technologies developed here include Nb-based superconducting circuits, microelectromechanical RF switches and mirrors, and an integrated, 0.35 µm, 3.3 V CCD/SOI CMOS process.

Packaging. Lincoln Laboratory also operates a fully equipped packaging facility capable of dicing wafers and developing and executing innovative packaging solutions on a variety of different device types.

Collaborations.  We have conducted collaborative research in the past with government, industry, and university partners using these facilities. Please contact us to find out more.

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