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Polyphase nonlinear equalization of time-interleaved analog-to-digital converters

Published in:
IEEE J. Sel. Top. Sig. Process., Vol. 3, No. 3, June 2009, pp. 362-373.

Summary

As the demand for higher data rates increases, commercial analog-to-digital converters (ADCs) are more commonly being implemented with multiple on-chip converters whose outputs are time-interleaved. The distortion generated by time-interleaved ADCs is now not only a function of the nonlinear behavior of the constituent circuitry, but also mismatches associated with interleaving multiple output streams. To mitigate distortion generated by time-interleaved ADCs, we have developed a polyphase NonLinear EQualizer (pNLEQ) which is capable of simultaneously mitigating distortion generated by both the on-chip circuitry and mismatches due to time interleaving. In this paper, we describe the pNLEQ architecture and present measurements of its performance.
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Summary

As the demand for higher data rates increases, commercial analog-to-digital converters (ADCs) are more commonly being implemented with multiple on-chip converters whose outputs are time-interleaved. The distortion generated by time-interleaved ADCs is now not only a function of the nonlinear behavior of the constituent circuitry, but also mismatches associated with...

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Extending the dynamic range of RF receivers using nonlinear equalization

Summary

Systems currently being developed to operate across wide bandwidths with high sensitivity requirements are limited by the inherent dynamic range of a receiver's analog and mixed-signal components. To increase a receiver's overall linearity, we have developed a digital NonLinear EQualization (NLEQ) processor which is capable of extending a receiver's dynamic range from one to three orders of magnitude. In this paper we describe the NLEQ architecture and present measurements of its performance.
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Summary

Systems currently being developed to operate across wide bandwidths with high sensitivity requirements are limited by the inherent dynamic range of a receiver's analog and mixed-signal components. To increase a receiver's overall linearity, we have developed a digital NonLinear EQualization (NLEQ) processor which is capable of extending a receiver's dynamic...

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A polyphase nonlinear equalization architecture and semi-blind identification method

Published in:
42th Asilomar Conf. on Signals, Systems, and Computers, 27 October 2008, pp. 593-597.

Summary

In this paper, we present an architecture and semiblind identification method for a polyphase nonlinear equalizer (pNLEQ). Such an equalizer is useful for extending the dynamic range of time-interleaved analog-to-digital converters (ADCs). Our proposed architecture is a polyphase extension to other architectures that partition the Volterra kernel into small nonlinear filters with relatively low computational complexity. Our semi-blind identification technique addresses important practical concerns in the equalizer identification process. We describe our architecture and demonstrate its performance with measured results when applied to a National Semiconductor ADC081000.
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Summary

In this paper, we present an architecture and semiblind identification method for a polyphase nonlinear equalizer (pNLEQ). Such an equalizer is useful for extending the dynamic range of time-interleaved analog-to-digital converters (ADCs). Our proposed architecture is a polyphase extension to other architectures that partition the Volterra kernel into small nonlinear...

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The cube coefficient subspace architecture for nonlinear digital predistortion

Published in:
42th Asilomar Conf. on Signals, Systems, and Computers, 27 October 2008, pp. 1857-1861.

Summary

In this paper, we present the cube coefficient subspace (CCS) architecture for linearizing power amplifiers (PAs), which divides the overparametrized Volterra kernel into small, computationally efficient subkernels spanning only the portions of the full multidimensional coefficient space with the greatest impact on linearization. Using measured results from a Q-Band solid state PA, we demonstrate that the CCS predistorter architecture achieves better linearization performance than state-of-the-art memory polynomials and generalized memory polynomials.
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Summary

In this paper, we present the cube coefficient subspace (CCS) architecture for linearizing power amplifiers (PAs), which divides the overparametrized Volterra kernel into small, computationally efficient subkernels spanning only the portions of the full multidimensional coefficient space with the greatest impact on linearization. Using measured results from a Q-Band solid...

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Variable projection and unfolding in compressed sensing

Published in:
Proc. 14th IEEE/SP Workshop on Statistical Signal Processing, 26-28 August 2007, pp. 358-362.

Summary

The performance of linear programming techniques that are applied in the signal identification and reconstruction process in compressed sensing (CS) is governed by both the number of measurements taken and the number of nonzero coefficients in the discrete basis used to represent the signal. To enhance the capabilities of CS, we have developed a technique called Variable Projection and Unfolding (VPU). VPU extends the identification and reconstruction capability of linear programming techniques to signals with a much greater number of nonzero coefficients in the basis in which the signals are compressible with significantly better reconstruction error.
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Summary

The performance of linear programming techniques that are applied in the signal identification and reconstruction process in compressed sensing (CS) is governed by both the number of measurements taken and the number of nonzero coefficients in the discrete basis used to represent the signal. To enhance the capabilities of CS...

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A new approach to achieving high-performance power amplifier linearization

Published in:
IEEE Radar Conf., 17-20 April 2007. doi: 10.1109/RADAR.2007.374329

Summary

Digital baseband predistortion (DBP) is not particularly well suited to linearizing wideband power amplifiers (PAs); this is due to the exorbitant price paid in computational complexity. One of the underlying reasons for the computational complexity of DBP is the inherent inefficiency of using a sufficiently deep memory and a high enough polynomial order to span the multidimensional signal space needed to mitigate PA-induced nonlinear distortion. Therefore we have developed a new mathematical method to efficiently search for and localize those regions in the multidimensional signal space that enable us to invert PA nonlinearities with a significant reduction in computational complexity. Using a wideband code division multiple access (CDMA) signal we demonstrate and compare the PA linearization performance and computational complexity of our algorithm to that of conventional DBP techniques using measured results.
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Summary

Digital baseband predistortion (DBP) is not particularly well suited to linearizing wideband power amplifiers (PAs); this is due to the exorbitant price paid in computational complexity. One of the underlying reasons for the computational complexity of DBP is the inherent inefficiency of using a sufficiently deep memory and a high...

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Nonlinear equalization for RF receivers

Published in:
Proc. Conf. on High Performance Computer Modernization Program, 26-29 June 2006, pp. 303-307.

Summary

This paper describes the need for High Performance Computing (HPC) to facilitate the development and implementation of a nonlinear equalizer that is capable of mitigating and/or eliminating nonlinear distortion to extend the dynamic range of radar front-end receivers decades beyond the analog state-of-the-art. The search space for the optimal nonlinear equalization (NLEQ) solution is computationally intractable using only a single desktop computer. However, we have been able to leverage a combination of an efficient greedy search with the high performance computing technologies of LLGrid and MatlabMPI to construct an NLEQ architecture that is capable of extending the dynamic range of Radar front-end receivers by over 25dB.
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Summary

This paper describes the need for High Performance Computing (HPC) to facilitate the development and implementation of a nonlinear equalizer that is capable of mitigating and/or eliminating nonlinear distortion to extend the dynamic range of radar front-end receivers decades beyond the analog state-of-the-art. The search space for the optimal nonlinear...

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