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Graphene-on-insulator transistors made using C on Ni chemical-vapor deposition

July 1, 2009
  |
Journal Article
Author:
Jakub T. Kedzierski
…
Published in:
IEEE Electron Device Lett., Vol. 30, No. 7, July 2009, pp. 745-747.
Topic:
fabrication
R&D area:

Summary

Graphene transistors are made by transferring a thin graphene film grown on Ni onto an insulating SiO2 substrate. The properties and integration of these graphene-on-insulator transistors are presented and compared to the characteristics of devices made from graphitized SiC and exfoliated graphene flakes.
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Summary

Graphene transistors are made by transferring a thin graphene film grown on Ni onto an insulating SiO2 substrate. The properties and integration of these graphene-on-insulator transistors are presented and compared to the characteristics of devices made from graphitized SiC and exfoliated graphene flakes.

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Graphene-on-insulator transistors made using C on Ni chemical-vapor deposition

Characterization of a three-dimensional SOI integrated-circuit technology

October 6, 2008
  |
Conference Paper
Author:
Chenson K. Chen
…
Published in:
2008 IEEE Int. SOI Conf. Proc., 6 October 2008, pp. 109-110.
Topic:
integrated circuit
R&D area:

Summary

At Lincoln Laboratory, we have established a three dimensional (3D) integrated circuit (IC) technology that has been developed and demonstrated over eight designs, bonding two or three active circuit layers or tiers to form monolithically integrated 3D circuits. This technology has been used to successfully demonstrate a large-area 8 x 8 mm2 high-3D-via-count 1024 x 1024 visible image, a 64 x 64 laser radar focal plane based on single-photon-sensitive avalanche photodiodes, and a 10Gb/s/pin low power interconnect for 3DICs. 3DIC technology in our most recently completed 3D multiproject (3DM2) run includes three active fully-depleted-SOI (FDSOI) circuit tiers, eleven interconnect-metal layers, and dense unrestricted 3D vias interconnecting stacked circuit layers, as shown in Figure 1. While we continue our efforts to scale our 3DIC technology and increase 3D via density, we are also working to improve our understanding of 3D integration impact on transistor and process monitor circuits. In this paper, we describe our process and test results after single tier circuit fabrication as well as after three-tier integration, determine impact of 3D vias on ring oscillator performance, and demonstrate functionality of single and multi-tier circuits of varying complexity.
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Summary

At Lincoln Laboratory, we have established a three dimensional (3D) integrated circuit (IC) technology that has been developed and demonstrated over eight designs, bonding two or three active circuit layers or tiers to form monolithically integrated 3D circuits. This technology has been used to successfully demonstrate a large-area 8 x...

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Characterization of a three-dimensional SOI integrated-circuit technology

Epitaxial graphene transistors on SiC substrates

August 1, 2008
  |
Journal Article
Author:
Jakub T. Kedzierski
…
Published in:
IEEE Trans. Electron Devices, Vol. 55, No. 8, August 2008, pp. 2078-2085.
Topic:
microelectronics
R&D area:

Summary

This paper describes the behavior of top-gated transistors fabricated using carbon, specifically epitaxial graphene on SiC, as the active material. Although graphene devices have been built before, in this paper, we provide the first demonstration and systematic evaluation of arrays of a large number of transistors produced using standard microelectronics methods. The graphene devices presented feature high-k dielectric, mobilities up to 5000 cm2/V · s, and Ion/Ioff ratios of up to seven, and are methodically analyzed to provide insight into the substrate properties. Typical of graphene, these micrometer-scale devices have negligible band gaps and, therefore, large leakage currents.
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Summary

This paper describes the behavior of top-gated transistors fabricated using carbon, specifically epitaxial graphene on SiC, as the active material. Although graphene devices have been built before, in this paper, we provide the first demonstration and systematic evaluation of arrays of a large number of transistors produced using standard microelectronics...

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Epitaxial graphene transistors on SiC substrates

A wafer-scale 3-D circuit integration technology

October 1, 2006
  |
Journal Article
Author:
James A. Burns
…
Published in:
IEEE Trans. Electron Devices, Vol. 53, No. 10, October 2006, pp. 2507-2516.
Topic:
integrated circuit
R&D area:
R&D group:

Summary

The rationale and development of a wafer-scale three-dimensional (3-D) integrated circuit technology are described. The essential elements of the 3-D technology are integrated circuit fabrication on silicon-on-insulator wafers, precision wafer-wafer alignment using an in-house-developed alignment system, low-temperature wafer-wafer bonding to transfer and stack active circuit layers, and interconnection of the circuit layers with dense-vertical connections with sub-[Omega] 3-D via resistances. The 3-D integration process is described as well as the properties of the four enabling technologies. The wafer-scale 3-D technology imposes constraints on the placement of the first lithographic level in a wafer-stepper process. Control of wafer distortion and wafer bow is required to achieve submicrometer vertical vias. Three-tier digital and analog 3-D circuits were designed and fabricated. The performance characteristics of a 3-D ring oscillator, a 1024 x 1024 visible imager with an 8-um pixel pitch, and a 64 x 64 Geiger-mode laser radar chip are described.
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Summary

The rationale and development of a wafer-scale three-dimensional (3-D) integrated circuit technology are described. The essential elements of the 3-D technology are integrated circuit fabrication on silicon-on-insulator wafers, precision wafer-wafer alignment using an in-house-developed alignment system, low-temperature wafer-wafer bonding to transfer and stack active circuit layers, and interconnection of the...

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A wafer-scale 3-D circuit integration technology

MEMS microswitches for reconfigurable microwave circuitry

March 1, 2001
  |
Journal Article
Author:
Sean M. Duffy
…
Published in:
IEEE Microw. Wirel. Compon. Lett., Vol. 11, No. 3, March 2001, pp. 106-108.
Topic:
antennas
R&D area:
R&D group:

Summary

The performance is reported for a new microelectromechanical structure (MEMS) cantilever microswitch. We report on both dc- and capacitively-contacted microswitches. The dc-contacted microswitches have contact resistance of less than 1 ohm, and the RF loss of the switch up to 40 GHz in the closed position is 0.1-0.2 dB. Capacitively-contacted switches have an impedance ratio of 141:1 from the open to closed state and in the closed position have a series capacitance of 1.2 pF. The capacitively-contacted switches have been measured up to 40 GHz with S(21) less than -0.7 dB across the 5-40 GHz band.
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Summary

The performance is reported for a new microelectromechanical structure (MEMS) cantilever microswitch. We report on both dc- and capacitively-contacted microswitches. The dc-contacted microswitches have contact resistance of less than 1 ohm, and the RF loss of the switch up to 40 GHz in the closed position is 0.1-0.2 dB. Capacitively-contacted...

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MEMS microswitches for reconfigurable microwave circuitry

Monolithic 3.3V CCD/SOI-CMOS Imager Technology

December 10, 2000
  |
Conference Paper
Author:
Vyshnavi Suntharalingam
…
Published in:
IEEE Int. Eelctron Devices Mtg., 10-13 December 2000, pp. 30.3.1-30.3.4.
Topic:
semiconductor (CMOS)
R&D area:
R&D group:

Summary

We have developed a merged CCD/SOI-CMOS technology that enables the fabrication of monolithic, low-power imaging systems on a chip. The CCD's, fabricated in the bulk handle wafer, have charge-transfer inefficiencies of about 1x10(-5) and well capacities of more than 100,000 electrons with 3.3-V clocks and 8x8um pixels. Fully depleted 0.35pm SOI-CMOS ring oscillators have stage delay of 48ps at 3.3V. We demonstrate for the first time an integrated image sensor with charge-domain A/D conversion and on-chip clocking.
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Summary

We have developed a merged CCD/SOI-CMOS technology that enables the fabrication of monolithic, low-power imaging systems on a chip. The CCD's, fabricated in the bulk handle wafer, have charge-transfer inefficiencies of about 1x10(-5) and well capacities of more than 100,000 electrons with 3.3-V clocks and 8x8um pixels. Fully depleted 0.35pm...

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Monolithic 3.3V CCD/SOI-CMOS Imager Technology
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