Publications

A digital focal plane array (DFPA) architecture has been developed that incorporates per-pixel full-dynamic-range analog-to-digital conversion and orthogonal-transfer-based realtime digital signal processing capability. Several long-wave infrared-optimized pixel processing focal plane readout integrated circuit (ROIC) designs have been implemented, each accommodating a 256 x 256 30-um-pitch detector array. Demonstrated in this paper is the application of this DFPA ROIC architecture to problems of background pedestal mitigation, wide-field imaging, image stabilization, edge detection, and velocimetry. The DFPA architecture is reviewed, and pixel performance metrics are discussed in the context of the application examples. The measured data reported here are for DFPA ROICs implemented in 90-nm CMOS technology and hybridized to HgxCd1-xTe (MCT) detector arrays with cutoff wavelengths ranging from 7 to 14.5 m and a specified operating temperature of 60 K-80 K.

Although CMOS technology scaling has provided tremendous power and circuit density benefits for innumerable applications, focal plane array (FPA) readouts have largely been left behind due to dynamic range and signal-to-noise considerations. However, if an appropriate pixel front end can be constructed to interface with a mostly digital pixel, it is possible to develop sensor architectures for which performance scales favorably with advancing technology nodes. Although the front-end design must be optimized to interface with a particular detector, the dominant back end architecture provides considerable potential for design reuse. In this work, digitally dominated long wave infrared (LWIR) active pixel sensors with cutoff wavelengths between 9 and 14.5 um are demonstrated. Two ROIC designs are discussed, each fabricated in a 90-nm digital CMOS process and implementing a 256 x 256 pixel array on a 30-um pitch. In one of the implemented designs, the feasibility of implementing a 15-um pixel pitch FPA with a 500 million electron effective well depth, less than 0.5% non-linearity in the target range and a measured NEdT of less than 50 mK at f/4 and 60 K is demonstrated. Simple on-FPA signal processing allows for a much reduced readout bandwidth requirement with these architectures. To demonstrate the potential for commonality that is offered by a digitally dominated architecture, this LWIR sensor design is compared and contrasted with other digital focal plane architectures. Opportunities and challenges for application of this approach to various detector technologies, optical wavelength ranges and systems are discussed.

The digital focal plane array (DFPA) project seeks to develop readout integrated circuits (ROICs) utilizing aggressively scaled and commercially available CMOS. Along with focal plane scaling and readout robustness benefits, the DFPA architecture provides a very simple way to implement processing algorithms directly on image data, in real-time, and prior to read-out of the data to an external digitizer or computer. In principle, almost any linear image processing filter kernel can be convolved with the scene image prior to readout. The useful size of the filter kernel is only limited by the size of the DFPA. Time domain filters can also be implemented on the ROIC to accomplish digital time domain integration (TDI) or change detection algorithms. The unique architecture can achieve the processing capability without the use of traditional digital adders or multipliers, like those used in most signal processors. Instead, a DFPA manipulates sequential digital counters under every pixel in a unique way to achieve the desired functionality. A non-addressable readout scheme is used for data transfer in four possible directions across the array. Although we are currently targeting longwave infrared (LWIR) applications, the approach can be potentially applied to any imaging application in any band.

The digital focal plane array (DFPA) project demonstrates the enabling technologies necessary to build readout integrated circuits for very large infrared focal plane arrays (IR FPAs). Large and fast FPAs are needed for a new class of spectrally diverse sensors. Because of the requirement for high-resolution (low noise) sampling, and because of the sample rate needed for rapid acquisition of high-resolution spectra, it is highly desirable to perform analog-to-digital (A/D) conversion right at the pixel level. A dedicated A/D converter located under every pixel in a one-million-plus element array, and all-digital readout integrated circuits will enable multi- and hyper-spectral imaging systems with unprecedented spatial and spectral resolution and wide area coverage. DFPAs provide similar benefits to standard IR imaging systems as well. We have addressed the key enabling technologies for realizing the DFPA architecture in this work. Our effort concentrated on demonstrating a 60-micron footprint, 14-bit A/D converter and 2.5 Gbps, 16:1 digital multiplexer, the most basic components of the sensor. The silicon test chip was fabricated in a 0.18- micron CMOS process, and was designed to operate with HgxCd1-xTe detectors at cryogenic temperatures. Two A/D designs, one using static logic and one using dynamic logic, were built and tested for performance and power dissipation. Structures for evaluating the bit-error-rate of the multiplexer on-chip and through a differential output driver were implemented for a complete performance assessment. A unique IC probe card with fixtures to mount into an evacuated, closed-cycle helium dewar were also designed for testing up to 2.5 Gbps at temperatures as low as 50 K.