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A fully integrated broadband sub-mmWave chip-to-chip interconnect

July 1, 2017
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Journal Article
Author:
Jack Holloway
…
Published in:
IEEE Trans. Microw. Theory Tech., Vol. 65, No. 7, July 2017, pp. 2373-86.
Topic:
integrated circuit
R&D area:
R&D group:

Summary

A new type of broadband link enabling extremely high-speed chip-to-chip communication is presented. The link is composed of fully integrated sub-mmWave on-chip traveling wave power couplers and a low-cost planar dielectric waveguide. This structure is based on a differentially driven half-mode substrate integrated waveguide supporting the first higher order hybrid microstrip mode. The cross-sectional width of the coupler structure is tapered in the direction of wave propagation to increase the coupling efficiency and maintain a large coupling bandwidth while minimizing its on-die size. A rectangular dielectric waveguide, constructed from Rogers Corporation R3006 material, is codesigned with the on-chip coupler structure to minimize coupling loss. The coupling structure achieves an average insertion loss of 4.8 dB from 220 to 270 GHz, with end-to-end link measurements presented. This system provides a packaging-friendly, cost effective, and high performance planar integration solution for ultrabroadband chip-to-chip communication utilizing millimeter waves.
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Summary

A new type of broadband link enabling extremely high-speed chip-to-chip communication is presented. The link is composed of fully integrated sub-mmWave on-chip traveling wave power couplers and a low-cost planar dielectric waveguide. This structure is based on a differentially driven half-mode substrate integrated waveguide supporting the first higher order hybrid...

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A fully integrated broadband sub-mmWave chip-to-chip interconnect

Fabrication process and properties of fully planarized deep-submicron Nb/Al-AlOx/Nb Josephson junctions for VLSI circuits

June 1, 2015
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Journal Article
Author:
Sergey K. Tolpygo
…
Published in:
IEEE Trans. Appl. Supercond., Vol. 25, No. 3, June 2015, 1101312.
Topic:
integrated circuit
R&D area:
R&D group:

Summary

A fabrication process for Nb/Al-AlOx/Nb Josephson junctions (JJs) with sizes down to 200 nm has been developed on a 200-mm-wafer tool set typical for CMOS foundry. This process is the core of several nodes of a roadmap for fully-planarized fabrication processes for superconductor integrated circuits with 4, 8, and 10 niobium layers developed at MIT Lincoln Laboratory. The process utilizes 248 nm photolithography, anodization, high-density plasma etching, and chemical mechanical polishing (CMP) for planarization of SiO2 interlayer dielectric. JJ electric properties and statistics such as on-chip and wafer spreads of critical current, Ic, normal-state conductance, GN, and run-to-run reproducibility have been measured on 200-mm wafers over a broad range of JJ diameters from 200 nm to 1500 nm and critical current densities, Jc, from 10 kA/cm^2 to 50 kA/cm^2 where the JJs become self-shunted. Diffraction-limited photolithography of JJs is discussed. A relationship between JJ mask size, JJ size on wafer, and the minimum printable size for coherent and partially coherent illumination has been worked out. The GN and Ic spreads obtained have been found to be mainly caused by variations of the JJ areas and agree with the model accounting for an enhancement of mask errors near the diffraction-limited minimum printable size of JJs. Ic and GN spreads from 0.8% to 3% have been obtained for JJs with sizes form 1500 nm down to 500 nm. The spreads increase to about 8% for 200-nm JJs. Prospects for circuit densities > 10^6 JJ/cm^2 and 193-nm photolithography for JJ definition are discussed.
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Summary

A fabrication process for Nb/Al-AlOx/Nb Josephson junctions (JJs) with sizes down to 200 nm has been developed on a 200-mm-wafer tool set typical for CMOS foundry. This process is the core of several nodes of a roadmap for fully-planarized fabrication processes for superconductor integrated circuits with 4, 8, and 10...

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Fabrication process and properties of fully planarized deep-submicron Nb/Al-AlOx/Nb Josephson junctions for VLSI circuits

Inductance of circuit structures for MIT LL superconductor electronics fabrication process with 8 niobium layers

June 1, 2015
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Journal Article
Author:
Sergey K. Tolpygo
…
Published in:
IEEE Trans. Appl. Supercond., Vol. 25, No. 3, 1 June 2015, 1100905.
Topic:
integrated circuit
R&D area:
R&D group:

Summary

Inductance of superconducting thin-film inductors and structures with linewidth down to 250 nm has been experimentally evaluated. The inductors include various striplines and microstrips, their 90 degree bends and meanders, interlayer vias, etc., typically used in superconducting digital circuits. The circuits have been fabricated by a fully planarized process with 8 niobium layers, developed at MIT Lincoln Laboratory for very-large-scale superconducting integrated circuits. Excellent run-to-run reproducibility and inductance uniformity of better than 1% across 200-mm wafers have been found. It has been found that the inductance per unit length of stripline and microstrip line inductors continues to grow as the inductor linewidth is reduced deep into the submicron range to the widths comparable to the film thickness and magnetic field penetration depth. It is shown that the linewidth reduction does not lead to widening of the parameter spread due to diminishing sensitivity of the inductance to the linewidth and dielectric thickness. The experimental results were compared with numeric inductance extraction using commercial software and freeware, and a good agreement was found for 3-D inductance extractors. Methods of further miniaturization of circuit inductors for achieving circuit densities >10^6 Josephson junctions per cm^2 are discussed.
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Summary

Inductance of superconducting thin-film inductors and structures with linewidth down to 250 nm has been experimentally evaluated. The inductors include various striplines and microstrips, their 90 degree bends and meanders, interlayer vias, etc., typically used in superconducting digital circuits. The circuits have been fabricated by a fully planarized process with...

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Inductance of circuit structures for MIT LL superconductor electronics fabrication process with 8 niobium layers

Materials and fabrication sequences for water soluble silicon integrated circuits at the 90 nm node

January 5, 2015
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Journal Article
Author:
Lan Yin
…
Published in:
Appl. Phys. Lett., Vol. 106, No. 1, 5 January 2015, 014105.
Topic:
integrated circuit
R&D area:
R&D group:

Summary

Tungsten interconnects in silicon integrated circuits built at the 90 nm node with releasable configurations on silicon on insulator wafers serve as the basis for advanced forms of water-soluble electronics. These physically transient systems have potential uses in applications that range from temporary biomedical implants to zero-waste environmental sensors. Systemic experimental studies and modeling efforts reveal essential aspects of electrical performance in field effect transistors and complementary ring oscillators with as many as 499 stages. Accelerated tests reveal timescales for dissolution of the various constituent materials, including tungsten, silicon, and silicon dioxide. The results demonstrate that silicon complementary metal-oxide-semiconductor circuits formed with tungsten interconnects in foundry-compatible fabrication processes can serve as a path to high performance, mass-produced transient electronic systems.
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Summary

Tungsten interconnects in silicon integrated circuits built at the 90 nm node with releasable configurations on silicon on insulator wafers serve as the basis for advanced forms of water-soluble electronics. These physically transient systems have potential uses in applications that range from temporary biomedical implants to zero-waste environmental sensors. Systemic...

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Materials and fabrication sequences for water soluble silicon integrated circuits at the 90 nm node

Energy efficiency benefits of subthreshold-optimized transistors for digital logic

October 6, 2014
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Conference Paper
Author:
Peter J. Grossmann
…
Published in:
2014 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conf. (S3S), 6-9 October 2014.
Topic:
integrated circuit
R&D area:
R&D group:

Summary

The minimum energy point of an integrated circuit (IC) is defined as the value of the supply voltage at which the energy per operation of the circuit is minimized. Several factors influence what the value of this voltage can be, including the topology of the circuit itself, the input activity factor, and the process technology in which the circuit is implemented. For application-specific ICs (ASICs), the minimum energy point usually occurs at a subthreshold supply voltage. Advances in subthreshold circuit design now permit correct circuit operation at, or even below, the minimum energy point. Since energy consumption is proportional to the square of the supply voltage, circuit design techniques and process technology choices that reduce the minimum energy point inherently improve the energy efficiency of ICs. Previous research has shown that optimizing process technology for subthreshold operation can improve IC energy efficiency. This, coupled with the energy efficiency advantages offered by fully-depleted silicon-on-insulator (FDSOI) processes, have led to the development of a subthreshold-optimized FDSOI process at MIT Lincoln Laboratory (MITLL) called xLP (Extreme Low Power). However, to date there has not been a quantitative estimate of the energy efficiency benefit of xLP or other analagous technology for complex digital circuits. This paper will show via simulation that the xLP process technology enables energy efficiency improvements that exceed that of process scaling by one generation. Specifically, the process is shown to improve power delay product by 57% vs. the IBM 90nm low power bulk process, and by 9% vs. the IBM 65 nm low power bulk technology at 0.3V.
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Summary

The minimum energy point of an integrated circuit (IC) is defined as the value of the supply voltage at which the energy per operation of the circuit is minimized. Several factors influence what the value of this voltage can be, including the topology of the circuit itself, the input activity...

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Energy efficiency benefits of subthreshold-optimized transistors for digital logic

Simultaneous dynamic pupil coding with on-chip coded aperture temporal imaging

June 13, 2014
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Conference Paper
Author:
Christy F. Cull
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Published in:
SRS 2014: Signal Recovery and Synthesis Conf., 13-17 June 2014.
Topic:
integrated circuit
R&D area:
R&D group:

Summary

We describe a new sensor that combines dynamic pupil coding with a digital readout integrated circuit (DROIC) capable of modulating a scene with a global or per-pixel time-varying, pseudo-random, and duo-binary signal (+1-1,0).
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Summary

We describe a new sensor that combines dynamic pupil coding with a digital readout integrated circuit (DROIC) capable of modulating a scene with a global or per-pixel time-varying, pseudo-random, and duo-binary signal (+1-1,0).

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Simultaneous dynamic pupil coding with on-chip coded aperture temporal imaging

On the development of a tileable LRU for the NextGen surveillance and weather radar capability program

October 15, 2013
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Conference Paper
Author:
M. David Conway
…
Published in:
2013 IEEE Int. Symp. On Phased Array Systems and Technology, 15-18 October 2013.
Topic:
integrated circuit
R&D area:
R&D group:

Summary

MIT Lincoln Laboratory is working towards the development of a tileable radar panel to satisfy multimission needs. A combination of custom and commercial off-the-shelf (COTS) Monolithic Microwave Integrated Circuits (MMICs) have been developed and/or employed to achieve the required system functionality. The integrated circuits (ICs) are integrated into a low cost T/R module compatible with commercial printed circuit board (PCB) manufacturing. Sixty-four of the transmit/receive (T/R) modules are integrated onto the aperture PCB in an 8x8 lattice. In addition to the T/R elements, the aperture PCB incorporates transmit and receive beamformers, power and logic distribution, and radiating elements. The aperture PCB is coupled with a backplane PCB to form a panel, the line replaceable unit (LRU) for the multifunction phased array radar (MPAR) initiative. This report summarizes the evaluation of the second iteration LRU aperture PCB and T/R element. Support fixturing was developed and paired with the panel to enable backplane functionality sufficient to support the test objective.
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Summary

MIT Lincoln Laboratory is working towards the development of a tileable radar panel to satisfy multimission needs. A combination of custom and commercial off-the-shelf (COTS) Monolithic Microwave Integrated Circuits (MMICs) have been developed and/or employed to achieve the required system functionality. The integrated circuits (ICs) are integrated into a low...

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On the development of a tileable LRU for the NextGen surveillance and weather radar capability program

A compressed sensing analog-to-information converter with edge-triggered SAR ADC core

May 20, 2012
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Journal Article
Author:
Michael G. Trakimas
…
Published in:
ISCAS 2012: IEEE Int. Symp. on Circuits and Systems, 20-23 May 2012, pp. 3162-3165.
Topic:
integrated circuit
R&D area:
R&D group:

Summary

This paper presents the design and implementation of an analog-to-information converter (AIC) based on compressed sensing. The core of the AIC is an edge-triggered charge-sharing SAR ADC. Compressed sensing is achieved through random sampling and asynchronous successive approximation conversion using the ADC core. Implemented in 90nm CMOS, the prototype SAR ADC core achieves a maximum sample rate of 9.5MS/s, an ENOB of 9.3 bits, and consumes 550 mu W from a 1.2V supply. Measurement results of the compressed sensing AIC demonstrate effective sub-Nyquist random sampling and reconstruction of signals with sparse frequency support suitable for wideband spectrum sensing applications. When accounting for the increased input bandwidth compared to Nyquist, the AIC achieves an effective FOM of 10.2fJ/conversion-step.
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Summary

This paper presents the design and implementation of an analog-to-information converter (AIC) based on compressed sensing. The core of the AIC is an edge-triggered charge-sharing SAR ADC. Compressed sensing is achieved through random sampling and asynchronous successive approximation conversion using the ADC core. Implemented in 90nm CMOS, the prototype SAR...

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A compressed sensing analog-to-information converter with edge-triggered SAR ADC core

Vertically stacked RF switches by wafer-scale three-dimensional integration

May 10, 2012
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Journal Article
Author:
Chang-Lee Chen
…
Published in:
Electron. Lett., Vol. 48, No. 10, 10 May 2012.
Topic:
integrated circuit
R&D area:

Summary

Vertically stacked RF switches implemented by wafer-scale three-dimensional (3D) integration of three completely fabricated silicon-on-insulator wafers are demonstrated. The individual switch performance was maintained through the 3D integration process while the signal path is shortened by vertical interconnects. The footprint of the switch can be shrunk in proportion to the number of tiers it is distributed between, demonstrating the potential of significant size reduction of multiple-throw switches commonly required in many applications.
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Summary

Vertically stacked RF switches implemented by wafer-scale three-dimensional (3D) integration of three completely fabricated silicon-on-insulator wafers are demonstrated. The individual switch performance was maintained through the 3D integration process while the signal path is shortened by vertical interconnects. The footprint of the switch can be shrunk in proportion to the...

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Vertically stacked RF switches by wafer-scale three-dimensional integration

Readout circuitry for continuous high-rate photon detection with arrays of InP Geiger-mode avalanche photodiodes

April 23, 2012
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Conference Paper
Author:
Jonathan P. Frechette
…
Published in:
SPIE, Vol. 8375, Advanced Photon Counting Techniques VI, 23 April 2012, 83750W.
Topic:
integrated circuit
R&D area:

Summary

An asynchronous readout integrated circuit (ROIC) has been developed for hybridization to a 32x32 array of single-photon sensitive avalanche photodiodes (APDs). The asynchronous ROIC is capable of simultaneous detection and readout of photon times of arrival, with no array blind time. Each pixel in the array is independently operated by a finite state machine that actively quenches an APD upon a photon detection event, and re-biases the device into Geiger mode after a programmable hold-off time. While an individual APD is in hold-off mode, other elements in the array are biased and available to detect photons. This approach enables high pixel refresh frequency (PRF), making the device suitable for applications including optical communications and frequency-agile ladar. A built-in electronic shutter that de-biases the whole array allows the detector to operate in a gated mode or allows for detection to be temporarily disabled. On-chip data reduction reduces the high bandwidth requirements of simultaneous detection and readout. Additional features include programmable single-pixel disable, region of interest processing, and programmable output data rates. State-based on-chip clock gating reduces overall power draw. ROIC operation has been demonstrated with hybridized InP APDs sensitive to 1.06-Mm and 1.55-Mm wavelength, and fully packaged focal plane arrays (FPAs) have been assembled and characterized.
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Summary

An asynchronous readout integrated circuit (ROIC) has been developed for hybridization to a 32x32 array of single-photon sensitive avalanche photodiodes (APDs). The asynchronous ROIC is capable of simultaneous detection and readout of photon times of arrival, with no array blind time. Each pixel in the array is independently operated by...

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Readout circuitry for continuous high-rate photon detection with arrays of InP Geiger-mode avalanche photodiodes
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