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Multi-Doppler Bin STAP

Geordi K. Borsari
MIT Lincoln Laboratory
244 Wood Street
Lexington, MA 02173-9108
email: borsari@ll.mit.edu

Abstract The Two-Bin Post-Doppler algorithm has been shown to provide excellent minimum detectable velocity (MDV) performance in a STAP processor. However implementation of such an algorithm also affects the training algorithm and the computational load on the STAP processor. The larger number of degrees-of-freedom associated with higher-order nulling algorithms sometimes forces non-local weight training when the conventional block range-segmented training approach is used. Therefore new training algorithms are needed for use with these higher-order algorithms. The Two-Bin nulling algorithm and the new training algorithms also require more computations. If this increased level of computations can not be supported by the signal processor, then methods of reducing the computation count must be investigated.

This presentation addresses these issues associated with attaining the MDV performance of the Two-Bin algorithm while simultaneously keeping the computational load manageable. The Two-Bin Post-Doppler nulling algorithm is reviewed and computationally efficient training algorithms are presented that complement the MDV attainable by the Two-Bin algorithm. Also presented is a variation of the Two-Bin algorithm called Dual-Port Two-Bin Nulling which achieves comparable MDV performance with a significant reduction in the computational load.



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