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THIRD ANNUAL
ASAP '95 WORKSHOP

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A Very-High-Performance
Scalable Digital
Beamforming Processor
Using VLSI Bit-Level
Systolic Array

William S. Song
MIT Lincoln Laboratory
244 Wood Street
Lexington, MA 02173-9108
email: song@ll.mit.edu

Abstract A very-high-performance digital beamforming processor for radar and communication applications has been developed by MIT Lincoln Laboratory. The processor is scalable in number of input channels, and performs a number of important radar functions requiring a large computational throughput. The VLSI digital filtering technology presented here is well suited for reducing the processor size, weight, and power consumption. Specific applications of interest are digital baseband conversion, digital in-phase/quadrature generation, channel equalization, and digital beamforming tasks. Furthermore, this technology is easily represented in a variety of software computer architectural design tools for migration into increased level of hardware complexity. The scalable cell library provides the upgrade path to reduced feature size and increased integration level.

The highly optimized CMOS VLSI bit-level systolic array cell library design gives the processor chip-set an extremely high performance. The current 4-channel demonstration board takes up only 6" x 4" board area and performs over 8 billion operations per second. An adaptive nulling scenario recorded with the RSTER (Radar Surveillance Technology Experimental Radar) equipment, including a simulated jammer and a test target, has been demonstrated on the processor. Since the total silicon die area of the 4-channel processor is less than 5 cm2, the whole processor area can be shrunk to a single multichip module of about 1 in2. The current chip-set uses 1.0 m CMOS technology, but the scalability of the cell library enables a much higher level of integration and performance with smaller device fabrication geometries.

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