STAP Processing on a
Distribution of 3-D Data
Sets and Processor
Allocation for Optimum

Mark F. Skalabrin and Thomas H. Einstein
Mercury Computer Systems, Inc.
199 Riverneck Road
Chelmsford, MA 01824-2820
tel: (508) 256-1300, ext. 348
fax: (508) 256-3599

Abstract In contrast to conventional two-dimensional radar processing, STAP processing is inherently three-dimensional (i.e., range/pulse/antenna-element).
Furthermore, real-time processing requirements for STAP typically range from 20--100 Gflops. Using current processor technology, processing requirements can only be met by using a multiprocessor system composed of several hundred interconnected compute elements (CEs). A major challenge in such an application is the distribution of the 3-D data set over the available CEs in the system. STAP processing generally entails at least three separate processing stages, i.e., one for each dimension of the 3-D data set. At each stage, data is distributed among the CEs for processing in parallel. This requires that entire vectors of data, along the dimension being processed at a given stage, be resident in the local memory of each CE. Each CE will process one or more vectors along the given processing dimension. The requisite redistribution of data between stages is called a distributed "corner-turn" and is affected by interprocessor communication. This paper describes a paradigm for distributing the 3-D STAP data set among the CEs in the multicomputer so as to maximize the efficiency of the interprocessor communications performed between stages. Specifically, the data is distributed so that the number of other CEs with which each CE has to communicate during any distributed "corner-turn" between stages is minimized. A further feature of the subject data distribution scheme is that the limiting number of CEs over which the 3-D STAP data may be distributed is increased to equal the product of the two smallest dimensions of the data set. This is especially important in STAP applications because of the large number of CEs required to satisfy the specified processing load.


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