LL Logo



STAP Implementation
Trades for a UHF
Airborne Early Warning
(AEW) Radar System

Robert M. Cooper
Lockheed Martin
P.O. Box 4840
Syracuse, NY 13221-4840
tel: (315) 456-2495
email: cooperr@syr.lmco.com

Abstract This presentation addresses the use of Space-Time Adaptive Processing (STAP) for clutter and jamming mitigation in a carrier based airborne early warning (AEW) radar system. A UHF, low PRF system has been chosen as the baseline, and the system is characterized by severe size, weight and power constraints, a relatively wide bandwidth and a rotating antenna, all of which effect the choice and implementation of a STAP algorithm. Broadband measured antenna data from the ADS-18S antenna, and realistic clutter models generated with the Rome Lab STAP Algorithm Development Tool (RLSTAP/ADT) are utilized to create simulated performance results. An overview of the fundamental characteristics of low PRF radars, alternative STAP clutter and jamming cancellation techniques, and a selection of candidate STAP architectures for detailed simulated performance comparisons are presented. Because of Doppler ambiguities inherent in a low PRF radar, platform motion compensation techniques over a sub-CPI become the preferred adaptive approach rather than spatial nulling for clutter cancellation. STAP performance with both narrow band and wideband models, and with both stationary and rotating antennas are used when comparing the interference mitigation capabilities of alternative STAP subsystem architectures. Finally, a summary of computational requirements for alternative STAP and signal processing implementations is presented. Tradeoffs with respect to the location of the pulse compressor before or after the STAP subsystem are presented in terms of computational requirements, STAP sample selection, and target cancellation concerns. The computational advantages of using a recursive QR decomposition algorithm such as the Recursive Modified Gram Schmidt (RMGS) algorithm rather than a block algorithm for a pre-Doppler STAP approach are explained. The implementation of this algorithm in a High Performance Scalable Computer implementation utilizing the Analog Devices SHARC processor and Myrinet LAN technology is summarized.



LL Logo Disclaimer

Direct comments and questions to: webmaster@ll.mit.edu

MIT Lincoln Laboratory. All rights reserved.