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FIFTH ANNUAL
ASAP '97 WORKSHOP


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Seeker Algorithm and
Architecture Study

Masahiro Arakawa and Robert A. Ford
MIT Lincoln Laboratory
244 Wood Street
Lexington, MA 02173-9108
tel: (781) 981-4906
email: masa@ll.mit.edu


Abstract
Missile seekers today must operate against increasingly elusive targets. These targets have inherently low radar signatures, operate at low altitudes, offering terrain masking and clutter, have variable flight paths, and employ countermeasures. Maintaining tracking performance despite these difficulties requires sophisticated signal processing. To improve their detection and tracking capabilities, seekers often use multiple modes. These multiple modes typically have many algorithmic commonalities. In this study, we explored the possibility of developing one processor architecture to handle both space-time adaptive processing (STAP) in the radar mode and single- and dual-frame image processing in the infrared (IR) mode. Specifically, we targeted commercial off-the-shelf (COTS) technology to reduce cost and technology insertion lag time, and parallel processors to exploit parallelism in the algorithms. Although a relaxation of the latency constraints on the signal processor makes coarse grain solutions possible, our analysis indicates that an investment commitment in miniaturization is necessary to close the gap between the processing densities available with state-of-the-art COTS parallel processors and the missiles' severe form factor requirements.

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