Subnanosecond CMOS Imager

Lincoln Laboratory has developed a 100 ps snapshot imager that will investigate the evolution of laser-imploded frozen hydrogen pellets that may be used for initiating controlled fusion.

The requirements of this imager pose some severe challenges:

Requirement
Challenge
Sensitive X-ray detection range 1 to 10 keV
Large resolution/pixel count >106 pixel imaging array
Simultaneous exposures in all pixels Signal delay across 2 cm array size = 66 ps at speed of light
Fast and adjustable sampling speeds 100 ps – 10ns
High current transients ~200 A peak
Wide dynamic range 10 bits

 

The device approach uses a separate complementary metal-oxide semiconductor (CMOS) readout integrated circuit (ROIC) bump-bonded to a custom silicon diode array fabricated at Lincoln Laboratory to achieve the necessary results. A cross section of the device is shown in Figure 1.

Figure 1. Cross-section drawing of CMOS 100 ps imager shows Si detector bump-bonded to readout circuit.Figure 1. Cross-section drawing of CMOS 100 ps imager shows Si detector bump-bonded to readout circuit. (Click on image to see larger version.)

The CMOS ROIC was designed and fabricated using a standard 0.18 µm foundry process, and benefiting from extensive industry development. The design produced less than 30 ps gate delays, and there are millions of transistors per chip. The device design was unusual in that both on-chip and in-pixel signal conditioning are needed to meet the requirements.

Figure 2. Readout circuit architecture. H-tree clock distribution methods were used to reduce clock skew, and four different types of pixel designs were used to provide the necessary signal conditioning.Figure 2. Readout circuit architecture. H-tree clock distribution methods were used to reduce clock skew, and four different types of pixel designs were used to provide the necessary signal conditioning. (Click on image to see larger version.)

The requirement for simultaneous sampling times in all pixels dictated an H-tree clock distribution (shown on the right side of Figure 2). Also, resources needed to be allocated throughout the device to amplify the clock signals and provide local capacitance to supply transient pulse current. This requirement meant that part of each pixel was dedicated to imaging functions (the aqua-colored portion) and part to clock regeneration (light-blue portion). Because clock regeneration needs varied according to the local region of the chip, four different pixel layouts were needed.

On a 64 × 64-pixel test circuit, clock skew was measured to be less than 3 ps peak to peak, and clock jitter less than 1.2 ps rms.

The Laboratory also developed a back-illuminated photodiode array of a unique design to meet the speed requirements. A cross section of the array is shown in Figure 3.

Figure 3. Cross section of diode sensor array. The array is designed to have very low internal resistance in the signal paths.Figure 3. Cross section of diode sensor array. The array is designed to have very low internal resistance in the signal paths. (Click on image to see larger version.)

The array thickness was chosen to optimize X-ray quantum efficiency and speed. We designed and fabricated unique through-device tungsten plugs to reduce internal resistance and increase the speed. The device used multiple metal layers and built-in capacitance structures to provide charge locally to minimize signal and bias line droop caused by the expected high peak currents from the transient photocarrier signal.

Subnanosecond imaging performance was demonstrated using an imaging diode on the CMOS array, with about 30 ps of jitter (most of this is not inherent to the imager). 

 

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