Deep-Depletion Imagers

Processing the high-resistivity (~ 5000 Ω-cm) silicon needed for deep-depletion imagers is challenging. To make high-resistivity silicon, most impurities have been removed from the material. However, some impurities are useful in limiting the spread of dislocations as a silicon device is processed at high temperatures and undergoes thermal stresses. Dislocations can give rise to increased dark current and decreased charge transfer efficiency. In processing high-resistivity silicon devices, careful attention must be paid to minimize stresses in the silicon during high temperature steps, for example, by using very slow ramp up and ramp down temperature changes, and special techniques are used to minimize any mechanical stresses on the device during high-temperature processing. Because of the care and time involved in processing high-resistivity silicon, most commercial devices tend to be fabricated from much lower-resistivity silicon material.

We have solved the problems of producing high-quality CCD devices on high-resistivity silicon with high yield and, in fact, use this material now for almost all the CCDs we now fabricate.

Figure 1. Design feature enables biasing of the substrate independently of device circuitryFigure 1. Design feature enables biasing of the substrate independently of device circuitry. (Click on image to see larger version.

The standard thickness for most Lincoln Laboratory–produced BI CCDs is about 45 µm. We have experimented making BI devices thicker in order to improve the QE for wavelengths greater than 900 nm. However, in this case, we use special techniques to ensure that the device is not only fully depleted but also has sufficiently strong drift fields to maintain a small (compared to the pixel size) charge point-spread function.

To supply the greater field, we have used a design feature that enables biasing of the substrate independently of the device circuitry, as shown in Figure 1.

We have fabricated and tested devices made at 75 µm thickness and shown that by using substrate bias we are able to fully deplete the device. To supply this back-to-front bias requires extra diodes and guard rings as shown in Figure 1.  This design change enables higher QE while also giving us the ability to maintain the charge point-spread function at a desired level.

 

 

 

 

 

 

 

 

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