Beyond CMOS Superconducting Digital Circuits

Technical Overview

As CMOS reaches the end of Moore's Law scaling there is a need to develop "beyond-CMOS" device technologies to achieve the next major leap in high-performance computing. Niobium (Nb)-based superconductive single-flux-quantum (SFQ) integrated circuit fabrication process technology is a leading candidate, offering a combination of high-speed and ultralow power dissipation unmatched by any other device. Lincoln Laboratory has been active in this field since the 1980s, and today has the most advanced SFQ process available. We are the foundry partner in the Intelligence Advanced Research Projects Activity (IARPA) Cryogenic Computing Complexity (C3) program, providing 4, 8, and 10 metal layer SFQ integrated circuit (IC) fabrication for the design partners in the program. This effort is aimed at demonstrating an SFQ technology to address the needs of exascale computing.

Operating at cryogenic temperatures, SFQ devices are based on physical phenomena unique to superconductive circuits, specifically the quantization of magnetic flux within a superconducting loop, and ultrahigh-speed Josephson junction (JJ) switching. Digital SFQ circuits involve the manipulation and storage of these flux quanta. While earlier SFQ research emphasized ultrahigh-speed operation, the current emphasis for computing applications has shifted toward energy efficiency and high levels of circuit integration. Recent advances in SFQ architectures have allowed researchers to develop small-scale, high-speed computational circuits that dissipate more than one thousand times less power (~ 10–18 J per logic operation) than state-of-the-art silicon CMOS circuits—a large energy advantage even after taking into account power for cryogenic cooling.

The Energy Efficient SFQ Road Map developed for the IARPA C3 programFigure 1. The Energy Efficient SFQ Road Map developed for the IARPA C3 program.

 

Program Goals

The goals of the SFQ fabrication process maturation are to progress down a five-node road map (Figure 1) leading to SFQ circuits with 1 million or more JJ devices. Building complex SFQ integrated circuits involves combining inductors for storing magnetic flux, JJs for control and switching, and wiring for connecting cells. The road map provides progressively more deeply scaled submicron features and an increasing number of wiring layers, enabling very compact high-speed circuits and high levels of integration. The third node calls for a 10-layer Nb process, with the cross section shown in Figure 2. The fourth and fifth nodes maintain a 10-layer process but reduce the minimum feature sizes to enable further increases in circuit density.

Cross-section of 10-Nb-layer SFQ microfabrication process Figure 2. Cross section of 10-Nb-layer SFQ microfabrication process under development at Lincoln Laboratory. The Josephson junction and resistor layers are indicated.

 

Research Highlights

Photomicrograph of an SFQ integrated circuit Figure 3. Photomicrograph of an SFQ integrated circuit (shown at partial completion for visibility) with key circuit elements indicated.

The SFQ circuits are fabricated on 8-inch silicon wafers with a single Josephson junction layer. Metal wiring layers are separated by dielectric, and vias are used to interconnect layers to form circuits. A separate resistive layer is deposited and patterned for shunt resistors. A photomicrograph of a small portion of an SFQ chip fabricated at Lincoln Laboratory in an eight-layer process is shown in Figure 3. Chemical mechanical planarization (CMP) is employed at various steps in the process to maintain yield and uniformity. The photomicrograph in Figure 4 showing a cross-section of our eight-layer Nb process illustrates the excellent uniformity that can be achieved through the use of CMP.

Photomicrograph of MIT Lincoln Laboratory 8-layer Nb SFQ integrated circuit processFigure 4. Photomicrograph of Lincoln Laboratory's eight-layer Nb SFQ integrated circuit process. Chemical mechanical planarization (CMP) is employed to achieve high uniformity.

Efforts are now under way with circuit design teams to exploit the features of this new fabrication process and advance the state of the art in demonstrated SFQ integrated circuits.

 

 

 

 

 

 

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