3D Integration of CMOS and Other Integrated Circuit Technologies

Technical Overview

Silicon on Insulator (SOI ) based wafer scale integration process flowFigure 1. Silicon-on-insulator (SOI)-based wafer-scale integration process flow. (Click on image to see larger version.)

The relentless increase in transistor count and circuit complexity in CMOS driven by Moore's Law is a testament to the semiconductor industry, which has managed to overcome many physical barriers that had been predicted to limit this trend. This increase is especially impressive considering that circuit technology has remained in two dimensions.

Expanding circuit density by using a third dimension is a comparatively little-explored path. Our group was among the early workers in this field. The approach starts with an oxide-to-oxide bond of the circuit layers on two silicon wafers. One wafer must be silicon-on-insulator (SOI) so that the bulk silicon wafer associated with it can be removed, stopping on the buried oxide (Figure 1). Vias are etched through circuit layer 2 down to circuit layer 1 and filled with metal to make electrical contact between the two circuit layers. This process can be repeated to integrate additional layers of active circuits.

The early work in this area was directed at connecting imager arrays to pixel-based readout circuits on pitches too small for conventional solder bump techniques (Figure 2). Latter technology development pushed to connect multiple CMOS tiers. Our group demonstrated unprecedented density in three-dimensioanl (3D) interconnects (Figure 3). The 3D interconnect pioneered by Lincoln Laboratory is still the highest density 3D interconnect yet demonstrated. There are many different ways to implement 3D integration with trade-offs both technical and economic in nature, but across the field there are two distinct advantages to 3D over conventional monolithic fabrication.

Cross-section SEM of smallest pixel pitch short wafer infrared (SWIR) imager Figure 2. Cross-section SEM of smallest pixel pitch short-wave infrared (SWIR) imager to date achieved by 3D integration of SW InGaAs detector layer with an SOI CMOS readout integrated circuit.

First, by vertically stacking circuits there can be a significant reduction in the length of metal interconnect lines, with a corresponding increase in circuit speed and decrease in power caused by line parasitic losses. Second, 3D integration allows the circuit designer to mix technologies and materials without compromising performance. The current trends in industry employ many integration technologies including 3D integration of memory integrated circuits (ICs) using micro-solder bumps, through-silicon-vias (TSVs), and interposer layers. Enhanced system capabilities, as well as reduced size, weight, and power (SWAP), can be realized by fabricating integrated circuit stacks using multiple integration technologies.

Cross-section SEM of three 150-nm 1.5V FDSOI CMOS TiersFigure 3. Cross-section SEM of three 150-nm 1.5V fully depleted SOI CMOS tiers showing oxide bonds and 3D via interconnects between circuit levels, including 3 transistor levels and 11 metal interconnect levels.


Program Goals

The current goals of the work in our group are to mature the 3D integration process and to develop low-cost and/or simpler integration approaches when permitted by the application. As the 3D integration using etched via technology matures, our work is branching out to include integration of silicon wafers with compound semiconductor wafers and integration of fully depleted SOI (FDSOI) CMOS wafers fabricated at Lincoln Laboratory with wafers fabricated at external foundries. Recently, techniques have been developed for the 3D integration of two circuit layers with a simpler face-to-face bond that simultaneously forms strong silicon dioxide bonds and metal contacts. In applications that only call for two circuit layers, this approach is highly reliable and costs less than the etched via process. We are exploring variants of this approach as well.

Research Highlights

Three-dimensional integration technologies developed in the Lincoln Laboratory Microelectronics Laboratory have been used to build two- and three-layer circuits for a number of applications, including imaging, signal processing, and computation (Figure 4).

History of 3D Integration at MIT Lincoln LaboratoryFigure 4. History of 3D integration at Lincoln Laboratory.


  • Advanced focal plane imaging arrays have been fabricated using Lincoln Laboratory's 3D integration technology combining SOI CMOS readout integrated circuits with either active pixel sensor arrays or single-photon-counting Geiger-mode avalanche photodiode (APD) arrays.
    • Fully parallel per-pixel analog-to-digital (A/D) conversion was first demonstrated on a two-tier 64 × 64 imager and subsequently on a three-tier 640 × 480 imager consisting of an imaging tier, an A/D conversion tier, and a digital signal processing tier.
    • Four-side-abuttable imaging modules for tiling large mosaic focal planes were fabricated in a two-tier 1024 × 1024—pixel design that demonstrated >1 million 3D vias with >99.999% via yield on a 8-mm pixel pitch.
    • Geiger-mode 3D LIDAR (light detection and ranging technology) arrays were achieved combining three different technologies: a 30-volt avalanche photodiode imaging tier, a 3.3-volt complementary metal-oxide semiconductor (CMOS) tier for APD control, and a 1.5-volt CMOS high-speed counter tier.
  • The 3D integration technology has been made available to the circuit-design research community through multiproject fabrication runs sponsored by the Defense Advanced Research Projects Agency. Three different multiproject runs have been completed and included more than 100 different circuit designs from 40 different research groups. Three-dimensional circuit concepts explored in these runs included stacked memories, field-programmable gate arrays, and mixed-signal and RF circuits.

  • The smallest pixel pitch shortwave infrared (SWIR) imager ever fabricated was achieved using high density heterogeneous 3D integration of an InGaAs detector to an SOI readout with both 8-µm and 6-µm pixel designs. "Wafer-Scale 3D integration of InGaAs Image Sensors with Si Readout Circuits" won the best paper award at the IEEE International 3D Systems Integration Conference in 2009.

  • Successful 3D integration of silicon (Si) CMOS readout ICs with externally fabricated technologies has enhanced our understanding of heterogeneous 3D integration issues including mixed-material, mixed-technology, and mixed-fabrication facility issues. Wafer-to-wafer heterogeneous 3D integration can enable improved system performance by enabling systems to use the best process technologies available for each functional tier in the 3D stack.


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