CMOS Technology

CMOS technology research in teh Quantum Information and Integrated Nanosystems Group focuses on development of novel microelectronics technologies in support of the current and future needs of the Department of Defense. These include
  • Extremely low-power technology for energy-starved systems
  • High-density 3D integration to enable highly integrated heterogeneous microsystems
  • Low-power readout circuits for extremely large focal plane arrays
  • Ultra-thin, flexible microelectronics for wearable or covert systems
  • Novel device technologies such as graphene-based transistors
xLP CMOS(left) Lincoln Laboratory silicon-on-insulator (SOI) CMOS. (right) Lincoln Laboratory extremely low-power (xLP) CMOS, cross-section view.

 

The CMOS technology area has a long history of supporting university research through government-sponsored multiproject wafer runs, in which circuits from external designers are fabricated in our unique CMOS technologies at no cost to the designer.

Our process is a fully depleted silicon-on-insulator (FDSOI) technology. Lincoln Laboratory was a pioneer in the development of FDSOI technology and is to our knowledge the only source of FDSOI technology within the U.S. government microelectronics community. FDSOI technology allows lower-power operation and increased radiation hardness compared to commercially available bulk-silicon microelectronics.

MIT LL High Density 3D-Integration Lincoln Laboratory high-density 3D-integration; stack of three circuit levels, cross-section view.

 

 

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