Low Leakage Readout Integrated Circuits

Technical Overview

Lincoln Laboratory has developed a custom high-voltage, low-leakage, fully depleted silicon-on-insulator (FDSOI) CMOS process enabling fabrication of readout integrated circuits (ROICs) for large-format, single-photon-sensitive, high-frame-rate imaging arrays in support of national security. ROIC requirements include fabrication on SOI for compatibility with the Laboratory's three-dimensional (3D) integration process, low-leakage CMOS to meet program-specific power requirements, 2.5-V CMOS to allow control of avalanche photodiodes (APDs), and a 25 x 25–mm chip size to accommodate a 1k x 1k imaging array. A survey of available foundry processes revealed none that were able to satisfy requirements of SOI, low-leakage, and chip-size, leading to selection of Lincoln Laboratory for ROIC fabrication.

The Laboratory's high-voltage, low-leakage CMOS process was developed by leveraging an existing baseline 90-nm FDSOI CMOS process, increasing gate-oxide thickness, adding specialized transistor geometries, optimizing transistor-channel-engineering implants and spacer width, and customizing layout design rules. This effort is enabled by the Laboratory's end-to-end integration capability, including design/layout, circuit fabrication, packaging, and testing, and a Microelectonics Laboratory with process flexibility not readily available in commercial fabrication facilities.

Program Goals

  • Develop a custom 2.5-V FDSOI CMOS process with <10 pA/mm leakage to enable fabrication of 1k x 1k ROICs
  • Validate front-end pixel circuit design and full ROIC functionality
  • Demonstrate yield of 500M-transistor ROIC circuits
  • Achieve 3D integration of ROIC and APD imaging array wafers using oxide-oxide bonding with wafer-to-wafer vertical interconnects

Research Highlights

Establishing a custom FDSOI CMOS process required thorough evaluation of our existing mainstream 90-nm baseline process in order to identify limitations and determine process and/or design solutions. To develop a 2.5-V low-leakage transistor ROIC process, we designed new test structures, executed a series of channel-engineering short-loop runs (to allow transistor performance evaluation and process optimization), established back-end yield capability, and then exercised all customized process modules in a fully integrated end-to-end CMOS fabrication run. Significant accomplishments included
  • Completing several transistor development runs to customize our baseline CMOS process to meet leakage and voltage requirements, allowing optimization of implant schedules, gate-oxide thickness, spacer width, and thermal budget,
  • Developing a split-gate device layout geometry that enabled 2.5-V operation with less than 10pA/mm leakage,
  • Creating and exercising a back-end-of-line metal-interconnect test mask to assess both random and systematic defects, and to establish back-end-of-line yield necessary to satisfy program deliverable goals,
  • Completing full CMOS fabrication and ROIC testing—validating transistor operating characteristics, pixel circuit design, and full circuit functionality.

 

 

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