xLP Low-Power CMOS

Technical Overview

A compelling variant of the fully depleted silicon-on-insulator (FDSOI) CMOS technology is the tuning of the transistors for extremely low-power (xLP) operation to enable a new class of electronics for energy-starved applications, such as unattended sensors, embedded medical devices, wearable electronics, and space-based systems. These applications often need modest processing power, but require extremely low static and active power dissipation.

Cross section of xLP transistorCross section of xLP transistor.

The most effective way of reducing power consumption of a digital circuit is to reduce the operating voltage below the threshold voltage of the transistor into the "subthreshold" regime. However, simply lowering the operating voltage of a conventional high-performance transistor will not produce an optimized ultralow-power transistor.

Conventional transistors will have comparatively high off-state leakage and overlap capacitance, as well as poorer subthreshold slope. In addition, device variation will severely limit the minimum operating voltage. These performance and reliability issues are addressed in the xLP program by developing a subthreshold-optimized transistor technology. After extensive process development and transistor integration, we are now fabricating the world's largest circuits optimized for subthreshold (low-voltage) operation.

Program Goals

xLP multiproject die with designs from 26 institutionsFigure 2. xLP multiproject die with designs from 26 institutions.

The Extremely Low-Power (xLP) CMOS Technology program will develop a transistor technology optimized for subthreshold operation, demonstrate the performance advantage through fabricated circuits, and make the process technology available to the low-power design community.

The first step is device engineering. There are four unique characteristics of the xLP transistors:

  1. Very low leakage (<10 pA/um) when the transistor is in the “off” state, which allows low static power dissipation.
  2. Near-ideal subthreshold swing, which allows the highest performance possible at extremely low operation voltage.
  3. Very low threshold voltage variation from device to device, which allows large-scale circuits to operate reliably at low voltage.
  4. Low device capacitance, which results in low switching energy and relatively fast switching, enabling a significant improvement in active power dissipation and operations/watt.

The xLP transistors achieve these characteristics by employing a FDSOI technology that allows excellent electrostatic control of the transistor channel and low capacitance, an undoped channel to reduce device variation, underlapped source/drain regions to further reduce capacitance, and a workfunction-tuned mid-gap metal gate for threshold voltage adjustment.

The next step is device fabrication, testing, and model development. We have fabricated thousands of xLP transistors in the Lincoln Laboratory Microelectronics Laboratory, test results from which have been used to develop SPICE (Simulation Program with Integrated Circuit Emphasis, an open-source program) models for the technology.  The SPICE models have been used to develop and characterize a complete set of standard cells for digital design. A Process Development Kit (PDK) is available for external users to design ultralow-power circuits in the Lincoln Laboratory xLP process technology.

Prototype subthreshold FPGAFigure 3: Prototype subthreshold FPGA.

The final step is circuit fabrication and performance characterization. Circuits of moderate size (tens of thousands of transistors) have been fabricated with functionality demonstrated at 300 mV and, in some cases, as low as 100 mV. Complex circuits designed both by the Lincoln Laboratory internal design community and the external circuit-design community have been fabricated. A full-size field-programmable gate array (FPGA) is currently in fabrication. We believe this is the largest subthreshold circuit ever fabricated and should set a new benchmark in ultralow-power FPGA performance. Examples of this subthreshold-optimized FPGA will be made available to the Department of Defense community for evaluation for use in prototype systems.

Research Highlights

  • xLP transistor technology achieves performance metrics of <10pA/um, <0.3 fF/μm, and Vt variation <10 mV.
  • SPICE models, standard cell library, and PDK were developed and made available to design community.
  • Defense Advanced Research Projects Agency (DARPA)–sponsored test run fabricated subthreshold-optimized circuits for Lincoln Laboratory and four external users.
  • DARPA-sponsored full multiproject run fabricated subthreshold-optimized circuits for the Laboratory and 26 external users.
  • Subthreshold Microelectronics Conference founded by Lincoln Laboratory provides a forum for technological exchange among the extremely low-power circuit and device technology community. The conference is now held annually as the IEEE SOI-3D-Subthreshold (S3S) Conference.
  • A novel circuit design for subthreshold FPGA was completed, along with development of new computer-aided design (CAD) tools for programming.
  • A prototype "mini" subthreshold FPGA was fabricated and demonstrated encouraging results from industry benchmark tests.
  • The world's first commercial-scale subthreshold FPGA is in fabrication, with results expected by the end of 2014.


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