Hybrid Photonic Integrated Circuits (PICs)

Technical Overview

A wide variety of different materials are utilized today to realize photonic components. Hybrid integration brings several different materials together on a common substrate to realize a photonic integrated circuit (PIC) that combines the best of each material system, such as III-V semiconductor materials for light generation and amplification, silicon waveguides for dense compact integration, dielectric waveguides for extremely low optical loss and high optical-damage thresholds, and electronics for control and feedback of the photonic system. Hybrid PICs can realize the ultimate in tight integration of many photonic components, and in doing so the system performance can be enhanced as interconnection losses are minimized and physical delays between optical components are reduced to a minimum. Additionally, new hybrid components can be realized that make use of all the materials' functionality within a single device.

Program Goals

  • Identify and define critical systems applications enabled by hybrid integration of photonic and electronic components
  • Investigate and develop advanced hybrid integration techniques to meet system requirements and facilitate rapid PIC prototyping
  • Provide the government with access to hybrid PIC design, fabrication, and packaging resources

Research Highlights

Lincoln Laboratory has been developing several hybrid techniques for integrating active components (e.g., lasers, optical amplifiers, optical modulators), passive components (e.g., waveguides, resonators, filters), and electronics. Three techniques have been developed:

  • Compound-semiconductor photonic components can be integrated onto a silicon photonic platform through bonding of unpatterned compound-semiconductor materials onto a PIC wafer on which passive waveguide structures have already been defined. This bonding can be done at the wafer scale or with chip-sized compound-semiconductor pieces. The hybrid PIC is then realized by removing the compound-semiconductor substrate and fabricating (i.e., patterning and metalizing) the compound-semiconductor components. An example of a hybrid silicon/compound-semiconductor laser is shown in Figure 1.

    Cleaved facet image of a hybrid Si / III-V laserFigure 1. Cleaved facet image of a hybrid Si / III-V laser. Light propagating in the silicon waveguide couples evanescently into the III-V material, where it can be amplified
    Here a completed passive silicon-photonic wafer was bonded to an InGaAsP (indium gallium arsenide phosphide) laser structure grown on an InP substrate. After bonding, the substrate of the InP wafer was removed leaving only the epitaxially grown InGaAsP layers on the silicon PIC. Subsequent processing steps define electrical contacts used to inject current into the laser structure. Light propagating in the silicon waveguide couples evanescently into the InGaAsP layers, where it is amplified. The advantage of this process is that many lasers can be realized simultaneously across the many die on a single wafer, with many lasers per die. The challenge of this process is achieving high yield for the III-V device processing.

  • In an alternative process, completed compound-semiconductor devices (or 1D arrays of devices) can be soldered directly onto a passive PIC die using pick-and-place tools. Shown in Figure 2 is a laser die soldered into an etched recess on a silicon substrate upon which dielectric waveguides have previously been fabricated.
    Schematic illustration and SEM images of a III-V die bonded onto a passive silicon PIC waferFigure 2. Schematic illustration and scanning electron microscope images of a III-V die bonded onto a passive silicon PIC wafer. (Click on image to see larger version.)

    Here light is coupled out the facet of the completed edge-emitting laser/amplifier structure and coupled into the dielectric waveguide through an etched facet in the dielectric layers. Intimate compact integration is attained between the laser structure and the PIC with potentially low optical loss in an extremely small form factor. This process is suitable for applications that require only a few compound-semiconductor components per die, and allows for prescreening of the devices prior to hybridization.

  • Dense integration of electronics and photonics can be accomplished with wafer-to-wafer bonding of a CMOS electronics wafer and a separate silicon photonics wafer. The two separately fabricated wafers are bonded face-to-face with oxide bonding. One of the substrates is subsequently removed and electrical vias can then be formed to interconnect the photonics layer to the electronics layer. Thus, extremely dense integration between the electronics and photonics is accomplished with very low parasitic capacitance (~1 fF) and excess delay, realizing performance levels that would not otherwise be possible. Shown in Figure 3 is a depiction of the bonding process and a pair of bonded eight-inch wafers after substrate removal.

    Schematic illustration of the wafer-to-wafer bonding between CMOS and photonics wafersFigure 3. Schematic illustration of the wafer-to-wafer bonding between CMOS and photonics wafers and image of the resulting eight-inch bonded wafer pair after removal of the substrate from the photonics wafer. (Click on image to view larger version.)





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