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Smart pixel imaging with computational-imaging arrays

Published in:
SPIE, Vol. 9070, Infrared Technology and Applications XL, 5 May 2014, 90703D.

Summary

Smart pixel imaging with computational-imaging arrays (SPICA) transfers image plane coding typically realized in the optical architecture to the digital domain of the focal plan array, thereby minimizing signal-to-noise losses associated with static filters or apertures and inherent diffraction concerns. MIT Lincoln Laboratory has been developing digital-pixel focal plane array (DFPA) devices for many years. In this work, we leverage legacy designs modified with new features to realize a computational imaging array (CIA) with advanced pixel-processing capabilities. We briefly review the use of DFPAs for on-chip background removal and image plane filtering. We focus on two digital readout integrated circuits (DROICS) as CIAs for two-dimensional (2D) transient target tracking and three-dimensional (3) transient target estimation using per-pixel coded-apertures or flutter shutters. This paper describes two DROICs -- a SWIR pixel-processing imager (SWIR-PPI) and a Visible CIA (VISCIA). SWIR-PPI is a DROIC with a 1 kHz global frame rate with a maximum per-pixel shuttering rate of 100 MHz, such that each pixel can be modulated by a time-varying, pseudo-random, and duo-binary signal (+1,-1,0). Combining per-pixel time-domain coding and processing enables 3D (x,y,T) target estimation with limited loss of spatial resolution. We evaluate structured and pseudo-random encoding strategies and employ linear inversion and non-linear inversion using total-variation minimization to estimate a 3D data cube from a single 2D temporally-encoded measurement. The VISCIA DROIC, while low-resolution, has a 6 kHz global frame rate and simultaneously encodes eight periodic or aperiodic transient target signatures at a maximum rate of 50 MHz using eight 8-bit counters. By transferring pixel-based image plane coding to the DROIC and utilizing sophisticated processing, our CIAs enable on-chip temporal super-resolution.
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Summary

Smart pixel imaging with computational-imaging arrays (SPICA) transfers image plane coding typically realized in the optical architecture to the digital domain of the focal plan array, thereby minimizing signal-to-noise losses associated with static filters or apertures and inherent diffraction concerns. MIT Lincoln Laboratory has been developing digital-pixel focal plane array...

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Sparse volterra systems: theory and practice

Published in:
Proc. IEEE Int. Conf. on Acoustics, Speech and Signal Processing, ICASSP, 25-31 May 2013.

Summary

Nonlinear effects limit analog circuit performance, causing both in-band and out-of-band distortion. The classical Volterra series provides an accurate model of many nonlinear systems, but the number of parameters grows extremely quickly as the memory depth and polynomial order are increased. Recently, concepts from compressed sensing have been applied to nonlinear system modeling in order to address this issue. This work investigates the theory and practice of applying compressed sensing techniques to nonlinear system identification under the constraints of typical radio frequency (RF) laboratories. The main theoretical result shows that these techniques are capable of identifying sparse Memory Polynomials using only single-tone training signals rather than pseudorandom noise. Empirical results using laboratory measurements of an RF receiver show that sparse Generalized Memory Polynomials can also be recovered from two-tone signals.
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Summary

Nonlinear effects limit analog circuit performance, causing both in-band and out-of-band distortion. The classical Volterra series provides an accurate model of many nonlinear systems, but the number of parameters grows extremely quickly as the memory depth and polynomial order are increased. Recently, concepts from compressed sensing have been applied to...

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Low power sparse polynomial equalizer (SPEQ) for nonlinear digital compensation of an active anti-alias filter

Published in:
Proc. 2012 IEEE Workshop on Signal Processing Systems, 17-19 October 2012, pp. 249-253.

Summary

We present an efficient architecture to perform on-chip nonlinear equalization of an anti-alias RF filter. The sparse polynomial equalizer (SPEq) achieves substantial power savings through co-design of the equalizer and the filter, which allows including the right number of processing elements, filter taps, and bits to maximize performance and minimize power consumption. The architecture was implemented in VHDL and fabricated in CMOS 65 nm technology. Testing results show that undesired spurs are suppressed to near the noise floor, improving the system's spur-free dynamic range by 25 dB in the median case, and consuming less than 12 mW of core power when operating at 200 MHz.
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Summary

We present an efficient architecture to perform on-chip nonlinear equalization of an anti-alias RF filter. The sparse polynomial equalizer (SPEq) achieves substantial power savings through co-design of the equalizer and the filter, which allows including the right number of processing elements, filter taps, and bits to maximize performance and minimize...

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On-chip nonlinear digital compensation for RF receiver

Published in:
HPEC 2011: Conf. on High Performance Embedded Computing, 21-22 September 2011.

Summary

A system-on-chip (SOC) implementation is an attractive solution for size, weight and power (SWaP) restricted applications, such as mobile devices and UAVs. This is partly because the individual parts of the system can be designed for a specific application rather than for a broad range of them, like commercial parts usually must be. Co-design of the analog hardware and digital processing further enhances the benefits of SOC implementations by allowing, for example, nonlinear digital equalization to further enhance the dynamic range of a given front-end component. This paper presents the implementation of nonlinear digital compensation for an active anti-aliasing filter, which is part of a low-power homodyne receiver design. The RF front-end circuitry and the digital compensation will be integrated in the same chip. Co-design allows the front-end to be designed with known dynamic range limitations that will later be compensated by nonlinear equalization. It also allows nonlinear digital compensation architectures matched to specific circuits and dynamic range requirements--while still maintaining some flexibility to deal with process variation--as opposed to higher power general purpose designs.
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Summary

A system-on-chip (SOC) implementation is an attractive solution for size, weight and power (SWaP) restricted applications, such as mobile devices and UAVs. This is partly because the individual parts of the system can be designed for a specific application rather than for a broad range of them, like commercial parts...

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An active filter achieving 43.6dBm OIP3

Published in:
IEEE Radio Frequency Integrated Circuits Symp., RFIC, 5-7 June 2011.

Summary

An active filter with a 50 omega buffer suitable as an anti-alias filter to drive a highly linear ADC is implemented in 0.13 um SiGe BiCMOS. This 6th-order Chebyshev filter has a 3 dB cutoff frequency of 28.3 MHz and achieves 36.5 dBm OIP3. Nonlinear digital equalization further improves OIP3 to 43.6 dBm. Measurements show 92 dB of rejection at the stopband and a gain of 49 dB. The measured in-band OIP3 of 43.6 dBm is 19 dB higher than previously published designs.
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Summary

An active filter with a 50 omega buffer suitable as an anti-alias filter to drive a highly linear ADC is implemented in 0.13 um SiGe BiCMOS. This 6th-order Chebyshev filter has a 3 dB cutoff frequency of 28.3 MHz and achieves 36.5 dBm OIP3. Nonlinear digital equalization further improves OIP3...

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Identification and compensation of Wiener-Hammerstein systems with feedback

Published in:
ICASSP 2011, IEEE Int. Conf. on Acoustics, Speech, and Signal Processing, 22-27 May 2011, pp. 4056-4059.

Summary

Efficient operation of RF power amplifiers requires compensation strategies to mitigate nonlinear behavior. As bandwidth increases, memory effects become more pronounced, and Volterra series based compensation becomes onerous due to the exponential growth in the number of necessary coefficients. Behavioral models such as Wiener-Hammerstein systems with a parallel feedforward or feedback filter are more tractable but more difficult to identify. In this paper, we extend a Wiener-Hammerstein identification method to such systems showing that identification is possible (up to inherent model ambiguities) from single- and two-tone measurements. We also calculate the Cramer-Rao bound for the system parameters and compare to our identification method in simulation. Finally, we demonstrate equalization performance using measured data from a wideband GaN power amplifier.
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Summary

Efficient operation of RF power amplifiers requires compensation strategies to mitigate nonlinear behavior. As bandwidth increases, memory effects become more pronounced, and Volterra series based compensation becomes onerous due to the exponential growth in the number of necessary coefficients. Behavioral models such as Wiener-Hammerstein systems with a parallel feedforward or...

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Physical layer considerations for wideband cognitive radio

Published in:
MILCOM 2010, IEEE Military Communications Conference , 31 October-3 November 2010, pp. 2113-2118.

Summary

Next generation cognitive radios will benefit from the capability of transmitting and receiving communications waveforms across many disjoint frequency channels spanning hundreds of megahertz of bandwidth. The information theoretic advantages of multi-channel operation for cognitive radio (CR), however, come at the expense of stringent linearity requirements on the analog transmit and receive hardware. This paper presents the quantitative advantages of multi-channel operation for next generation CR, and the advanced digital compensation algorithms to mitigate transmit and receive nonlinearities that enable broadband multi-channel operation. Laboratory measurements of the improvement in the performance of a multi-channel CR communications system operating below 2 GHz in over 500 MHz of instantaneous bandwidth are presented.
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Summary

Next generation cognitive radios will benefit from the capability of transmitting and receiving communications waveforms across many disjoint frequency channels spanning hundreds of megahertz of bandwidth. The information theoretic advantages of multi-channel operation for cognitive radio (CR), however, come at the expense of stringent linearity requirements on the analog transmit...

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Variable projection and unfolding in compressed sensing

Published in:
Proc. 14th IEEE/SP Workshop on Statistical Signal Processing, 26-28 August 2007, pp. 358-362.

Summary

The performance of linear programming techniques that are applied in the signal identification and reconstruction process in compressed sensing (CS) is governed by both the number of measurements taken and the number of nonzero coefficients in the discrete basis used to represent the signal. To enhance the capabilities of CS, we have developed a technique called Variable Projection and Unfolding (VPU). VPU extends the identification and reconstruction capability of linear programming techniques to signals with a much greater number of nonzero coefficients in the basis in which the signals are compressible with significantly better reconstruction error.
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Summary

The performance of linear programming techniques that are applied in the signal identification and reconstruction process in compressed sensing (CS) is governed by both the number of measurements taken and the number of nonzero coefficients in the discrete basis used to represent the signal. To enhance the capabilities of CS...

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