Publications
Back-illuminated three-dimensionally integrated CMOS image sensors for scientific applications
Summary
Summary
SOI-based active pixel image sensors have been built in both monolithic and vertically interconnected pixel technologies. The latter easily supports the inclusion of more complex pixel circuitry without compromising pixel fill factor. A wafer-scale back-illumination process is used to achieve 100% fill factor photodiodes. Results from 256 x 256 and...
A wafer-scale 3-D circuit integration technology
Summary
Summary
The rationale and development of a wafer-scale three-dimensional (3-D) integrated circuit technology are described. The essential elements of the 3-D technology are integrated circuit fabrication on silicon-on-insulator wafers, precision wafer-wafer alignment using an in-house-developed alignment system, low-temperature wafer-wafer bonding to transfer and stack active circuit layers, and interconnection of the...
Laser radar imager based on 3D integration of Geiger-mode avalanche photodiodes with two SOI timing circuit layers
Summary
Summary
We have developed focal-plane arrays and laser-radar (ladar) imaging systems based on Geiger-mode avalanche photodiodes (APDs) integrated with high-speed all-digital CMOS timing circuits. A Geiger-mode APD produces a digital pulse upon detection of a single photon. This pulse is used to stop a fast digital counter in the pixel circuit...
CMOS detector technology
Summary
Summary
An entry level overview of state-of-the-art CMOS detector technology is presented. Operating principles and system architecture are explained in comparison to the well-established CCD technology, followed by a discussion of important benefits of modern CMOS-based detector arrays. A number of unique CMOS features including different shutter modes and scanning concepts...
Megapixel CMOS image sensor fabricated in three-dimensional integrated circuit technology
Summary
Summary
In this paper a 3D integrated 1024x1024, 8um pixel visible image sensor fabricated with oxide-to-oxide wafer bonding and 2-um square 3-D-vias in every pixel is presented. The 150mm wafer technology integrates a low-leakage, deep-depletion, 100% fill factor photodiode layer to a 3.3-V, 0.35-um gate length fully depleted (FD) SOI CMOS...
Silicon-on-insulator-based single-chip image sensors: low-voltage scientific imaging
Summary
Summary
A low-voltage (
Monolithic 3.3V CCD/SOI-CMOS Imager Technology
Summary
Summary
We have developed a merged CCD/SOI-CMOS technology that enables the fabrication of monolithic, low-power imaging systems on a chip. The CCD's, fabricated in the bulk handle wafer, have charge-transfer inefficiencies of about 1x10(-5) and well capacities of more than 100,000 electrons with 3.3-V clocks and 8x8um pixels. Fully depleted 0.35pm...
SOI wafer selection for CCD/SOI-CMOS technology [Abstract]
Summary
Summary
We have developed a process that monolithically integrates fully depleted SOI CMOS (FDSOI) with high-performance CCD image sensors. This integrated technology that enables charged-coupled devices (CCD's) to be in close proximity to, yet isolated from, FDSOI circuits. This approach exploits both the advantages of FDSOI (fast, low-power CMOS with potentially...