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Fabrication process and properties of fully planarized deep-submicron Nb/Al-AlOx/Nb Josephson junctions for VLSI circuits

Published in:
IEEE Trans. Appl. Supercond., Vol. 25, No. 3, June 2015, 1101312.

Summary

A fabrication process for Nb/Al-AlOx/Nb Josephson junctions (JJs) with sizes down to 200 nm has been developed on a 200-mm-wafer tool set typical for CMOS foundry. This process is the core of several nodes of a roadmap for fully-planarized fabrication processes for superconductor integrated circuits with 4, 8, and 10 niobium layers developed at MIT Lincoln Laboratory. The process utilizes 248 nm photolithography, anodization, high-density plasma etching, and chemical mechanical polishing (CMP) for planarization of SiO2 interlayer dielectric. JJ electric properties and statistics such as on-chip and wafer spreads of critical current, Ic, normal-state conductance, GN, and run-to-run reproducibility have been measured on 200-mm wafers over a broad range of JJ diameters from 200 nm to 1500 nm and critical current densities, Jc, from 10 kA/cm^2 to 50 kA/cm^2 where the JJs become self-shunted. Diffraction-limited photolithography of JJs is discussed. A relationship between JJ mask size, JJ size on wafer, and the minimum printable size for coherent and partially coherent illumination has been worked out. The GN and Ic spreads obtained have been found to be mainly caused by variations of the JJ areas and agree with the model accounting for an enhancement of mask errors near the diffraction-limited minimum printable size of JJs. Ic and GN spreads from 0.8% to 3% have been obtained for JJs with sizes form 1500 nm down to 500 nm. The spreads increase to about 8% for 200-nm JJs. Prospects for circuit densities > 10^6 JJ/cm^2 and 193-nm photolithography for JJ definition are discussed.
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Summary

A fabrication process for Nb/Al-AlOx/Nb Josephson junctions (JJs) with sizes down to 200 nm has been developed on a 200-mm-wafer tool set typical for CMOS foundry. This process is the core of several nodes of a roadmap for fully-planarized fabrication processes for superconductor integrated circuits with 4, 8, and 10...

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Inductance of circuit structures for MIT LL superconductor electronics fabrication process with 8 niobium layers

Summary

Inductance of superconducting thin-film inductors and structures with linewidth down to 250 nm has been experimentally evaluated. The inductors include various striplines and microstrips, their 90 degree bends and meanders, interlayer vias, etc., typically used in superconducting digital circuits. The circuits have been fabricated by a fully planarized process with 8 niobium layers, developed at MIT Lincoln Laboratory for very-large-scale superconducting integrated circuits. Excellent run-to-run reproducibility and inductance uniformity of better than 1% across 200-mm wafers have been found. It has been found that the inductance per unit length of stripline and microstrip line inductors continues to grow as the inductor linewidth is reduced deep into the submicron range to the widths comparable to the film thickness and magnetic field penetration depth. It is shown that the linewidth reduction does not lead to widening of the parameter spread due to diminishing sensitivity of the inductance to the linewidth and dielectric thickness. The experimental results were compared with numeric inductance extraction using commercial software and freeware, and a good agreement was found for 3-D inductance extractors. Methods of further miniaturization of circuit inductors for achieving circuit densities >10^6 Josephson junctions per cm^2 are discussed.
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Summary

Inductance of superconducting thin-film inductors and structures with linewidth down to 250 nm has been experimentally evaluated. The inductors include various striplines and microstrips, their 90 degree bends and meanders, interlayer vias, etc., typically used in superconducting digital circuits. The circuits have been fabricated by a fully planarized process with...

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Reconfigurable RF systems using commercially available digital capacitor arrays

Published in:
38th Annual GOMACTech Conf., 11-14 March 2013.
R&D group:

Summary

Various RF circuit blocks implemented by using commercially available MEMS digital capacitor arrays are presented for reconfigurable RF systems. The designed circuit blocks are impedance-matching network, tunable bandpass filter, and VSWR sensor. The frequency range of the designed circuits is 0.4-4GHz. The MEMS digital capacitor arrays that are employed in the designs have built-in dc-to-dc voltage converter and serial interface significantly simplifying the control circuitry. The RF circuit blocks are suitable to low-cost, high-level of integration, thanks to the commercially available parts and standard RF packaging technologies.
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Summary

Various RF circuit blocks implemented by using commercially available MEMS digital capacitor arrays are presented for reconfigurable RF systems. The designed circuit blocks are impedance-matching network, tunable bandpass filter, and VSWR sensor. The frequency range of the designed circuits is 0.4-4GHz. The MEMS digital capacitor arrays that are employed in...

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Circuit-fed tile-approach configuration for millimeter-wave spatial power combining

Published in:
IEEE Trans. Microw. Theory Tech., Vol. 50, No. 1, Part 1, January 2002, pp. 17-21.

Summary

In this paper, a circuit-fed spatially combined transmitter array is described for operation at 44 GHz. The array contains 256 elements where each element consists of a monolithic-microwave integrated-circuit amplifier and a circularly polarized microchip patch antenna. The array is constructed using 16-element tile-approach subarrays. Each subarray is a two RF-level (three-dimensional) multichip module containing integrated microstrip patch antennas. The basic construction of the transmitter array resembles tile-approach phased arrays; however, the implementation has been tailored for the power-combining application. The peak performance at 43.5 GHz is equivalent isotropic radiated power of 40.6 dBW (11570 W), effective transmitted power (Peff) of 5.9 W, dc-to-RF efficiency of 7.3%, and system gain of 35 dB.
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Summary

In this paper, a circuit-fed spatially combined transmitter array is described for operation at 44 GHz. The array contains 256 elements where each element consists of a monolithic-microwave integrated-circuit amplifier and a circularly polarized microchip patch antenna. The array is constructed using 16-element tile-approach subarrays. Each subarray is a two...

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MEMS microswitches for reconfigurable microwave circuitry

Summary

The performance is reported for a new microelectromechanical structure (MEMS) cantilever microswitch. We report on both dc- and capacitively-contacted microswitches. The dc-contacted microswitches have contact resistance of less than 1 ohm, and the RF loss of the switch up to 40 GHz in the closed position is 0.1-0.2 dB. Capacitively-contacted switches have an impedance ratio of 141:1 from the open to closed state and in the closed position have a series capacitance of 1.2 pF. The capacitively-contacted switches have been measured up to 40 GHz with S(21) less than -0.7 dB across the 5-40 GHz band.
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Summary

The performance is reported for a new microelectromechanical structure (MEMS) cantilever microswitch. We report on both dc- and capacitively-contacted microswitches. The dc-contacted microswitches have contact resistance of less than 1 ohm, and the RF loss of the switch up to 40 GHz in the closed position is 0.1-0.2 dB. Capacitively-contacted...

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Combining-efficiency X-band spatial power-combined array using a multilayered packaging architecture

Author:
Published in:
IEEE Trans. Microw. Theory Tech., Vol. 48, No. 10, October 2000, pp. 1769-1771.

Summary

The design of a high combining-efficiency spatial power-combined array is described in this paper. A multilayered stacked stripline architecture enables a compact stable design. An array incorporating antenna active impedance and proper amplifier matching is measured with a combining efficiency of 87%, radiating 6.8 W of an available 7.8 W into the ideal uniformly illuminated array directivity at 10.1 GHz.
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Summary

The design of a high combining-efficiency spatial power-combined array is described in this paper. A multilayered stacked stripline architecture enables a compact stable design. An array incorporating antenna active impedance and proper amplifier matching is measured with a combining efficiency of 87%, radiating 6.8 W of an available 7.8 W...

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MEMs microswitch arrays for reconfigurable distributed microwave components

Summary

A revolutionary device technology and circuit concept is introduced for a new class of reconfigurable microwave circuits and antennas. The underlying mechanism is a compact MEMs cantilever microswitch that is arrayed in two-dimensions. The switches have the ability to be individually actuated. By constructing distributed circuit components from an array, the individual addressability of the microswitch provides the means to reconfigure the circuit trace and, thus, provides the ability to either fine-tune or completely reconfigure the circuit element's behavior. Device performance can be reconfigured over a decade in bandwidth in the nominal frequency range of 1 to 100 GHz. In addition, other circuit-element attributes can be reconfigured such as instantaneous bandwidth, impedance, and polarization (for antennas). This will enable the development of next-generation communication, radar and surveillance systems with agiIity to reconfigure operation for diverse operating bands, modes, power levels, and waveforms.
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Summary

A revolutionary device technology and circuit concept is introduced for a new class of reconfigurable microwave circuits and antennas. The underlying mechanism is a compact MEMs cantilever microswitch that is arrayed in two-dimensions. The switches have the ability to be individually actuated. By constructing distributed circuit components from an array...

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A modified transmission line model for cavity backed microstrip antennas

Author:
Published in:
IEEE Antennas and Propagation Society Int. Symp. 1997 Digest, Vol. 4, 13-18 July 1997, pp. 2139-42.

Summary

Spatial power combining of many MMIC amplifiers at millimeter wave frequencies using a fixed array of microstrip antenna elements places unique demands on dielectric media. The substrate must be relatively thick to allow space for MMIC placement, must provide rather high thermal conductivity to disipate MMIC heat, and be of high dielectric constant to shrink circuit element dimensions. Presently, microstrip antenna models require a low dielectric constant substrate to be valid. This paper presents a modified transmission line model on the model of Pues and Van de Capelle which addresses the problems of thick, high microstrip antenna elements. The goal of the model was to guide design of a microstrip array antenna suitable for a spatial power combined module.
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Summary

Spatial power combining of many MMIC amplifiers at millimeter wave frequencies using a fixed array of microstrip antenna elements places unique demands on dielectric media. The substrate must be relatively thick to allow space for MMIC placement, must provide rather high thermal conductivity to disipate MMIC heat, and be of...

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45-GHz MMIC power combining using a circuit-fed, spatially combined array

Published in:
IEEE Microw. Guid. Wave Lett., Vol. 7, No. 1, January 1997, pp. 15-17.

Summary

We describe the design and measurement of a hybrid-circuit, tile-approach subarray for use in spatial power-combined transmitters. The subarray consists of 16 monolithic millimeter-wave integrated circuit (MMIC) amplifiers, each feeding a circularly polarized cavity-backed microstrip antenna. The average performance across the 43.5-45.5 GHz band is as follows: EIRP 18.3 dBW, dc-RF efficiency 10.3%, effective transmitter power 530 mW, system gain 13.2 dB, and combining efficiency of 46.2%. The minimum axial ratio is 1.2 dB at 43.9 GHz, and the array has a 3% 3-dB axial ratio bandwidth.
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Summary

We describe the design and measurement of a hybrid-circuit, tile-approach subarray for use in spatial power-combined transmitters. The subarray consists of 16 monolithic millimeter-wave integrated circuit (MMIC) amplifiers, each feeding a circularly polarized cavity-backed microstrip antenna. The average performance across the 43.5-45.5 GHz band is as follows: EIRP 18.3 dBW...

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A 16-element subarray for hybrid-circuit tile-approach spatial power combining

Published in:
IEEE Trans. Microw. Theory Tech., Vol. 44, No. 11, November 1996, pp. 2093-8.

Summary

Three designs for a 4-by-4 are described for use in a spatial power-combined transmitter. The subarrays are constructed using a hybrid-circuit, tile-approach architecture and are composed of 16 cavity-backed, proximity-coupled microstrip antennas, each fed by a 0.5 watt amplifier. Both linearly and circularly polarized subarrays have been constructed for operation over a 10% band centered at 10 GHz. The linearly polarized subarray showed the following peak performance: EIRP greater than 27 dBW, effective transmitter power greater than 5 watts, dc-RF efficiency greater than 20%, and excellent graceful degradation performance.
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Summary

Three designs for a 4-by-4 are described for use in a spatial power-combined transmitter. The subarrays are constructed using a hybrid-circuit, tile-approach architecture and are composed of 16 cavity-backed, proximity-coupled microstrip antennas, each fed by a 0.5 watt amplifier. Both linearly and circularly polarized subarrays have been constructed for operation...

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