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Radiation effects in 3D integrated SOI SRAM circuits
Summary
Summary
Radiation effects are presented for the first time for vertically integrated 3 x 64 -kb SOI SRAM circuits fabricated using the 3D process developed at MIT Lincoln Laboratory. Three fully-fabricated 2D circuit wafers are stacked using standard CMOS fabrication techniques including thin-film planarization, layer alignment and oxide bonding. Micron-scale dense...
SET characterization in logic circuits fabricated in a 3DIC technology
Summary
Summary
Single event transients are characterized for the first time in logic gate circuits fabricated in a novel 3DIC technology where SET test circuits are vertically integrated on three tiers in a 20-um-thick layer. This 3D technology is extremely will suited for high-density circuit integration because of the small dimension the...
FDSOI process technology for subthreshold-operation ultra-low power electronics
Summary
Summary
Ultralow-power electronics will expand the technological capability of handheld and wireless devices by dramatically improving battery life and portability. In addition to innovative low-power design techniques, a complementary process technology is required to enable the highest performance devices possible while maintaining extremely low power consumption. Transistors optimized for subthreshold operation...
SOI-enabled three-dimensional integrated-circuit technology
Summary
Summary
We have demonstrated a new 3D device interconnect approach, with direct back side via connection to a transistor in a 3D stack, resulting in a reduced 3D footprint by an estimated ~40% as well as potential for lower series resistance. We have demonstrated high yield 3D through-oxide-via (TOV) with a...
FDSOI process technology for subthreshold-operation ultralow-power electronics
Summary
Summary
Ultralow-power electronics will expand the technological capability of handheld and wireless devices by dramatically improving battery life and portability. In addition to innovative low-power design techniques, a complementary process technology is required to enable the highest performance devices possible while maintaining extremely low power consumption. Transistors optimized for subthreshold operation...
Three-dimensional integration technology for advanced focal planes
Summary
Summary
We have developed a three-dimensional (3D) circuit integration technology that exploits the advantages of silicon-on-insulator (SOI) technology to enable wafer-level stacking and micrometer-scale electrical interconnection of fully fabricated circuit wafers. This paper describes the 3D technology and discusses some of the advanced focal plane arrays that have been built using...
Time delay integration and in-pixel spatiotemporal filtering using a nanoscale digital CMOS focal plane readout
Summary
Summary
A digital focal plane array (DFPA) architecture has been developed that incorporates per-pixel full-dynamic-range analog-to-digital conversion and orthogonal-transfer-based realtime digital signal processing capability. Several long-wave infrared-optimized pixel processing focal plane readout integrated circuit (ROIC) designs have been implemented, each accommodating a 256 x 256 30-um-pitch detector array. Demonstrated in this...
Wafer-scale 3D integration of InGaAs image sensors with Si readout circuits
Summary
Summary
In this work, we modified our wafer-scale 3D integration technique, originally developed for Si, to hybridize InP-based image sensor arrays with Si readout circuits. InGaAs image arrays based on the InGaAs layer grown on InP substrates were fabricated in the same processing line as silicon-on-insulator (SOI) readout circuits. The finished...
Characterization of a three-dimensional SOI integrated-circuit technology
Summary
Summary
At Lincoln Laboratory, we have established a three dimensional (3D) integrated circuit (IC) technology that has been developed and demonstrated over eight designs, bonding two or three active circuit layers or tiers to form monolithically integrated 3D circuits. This technology has been used to successfully demonstrate a large-area 8 x...
InP-based single-photon detector arrays with asynchronous readout integrated circuits
Summary
Summary
We have developed and demonstrated a highduty- cycle asynchronous InGaAsP-based photon counting detector system with near-ideal Poisson response, roomtemperature operation, and nanosecond timing resolution for near-infrared applications. The detector is based on an array of Geiger-mode avalanche photodiodes coupled to a custom integrated circuit that provides for lossless readout via...