Two-Phase Helium Convection Loop for Cryogenic Cooling

The development of superconducting and low-temperature circuitry necessitates rigorous testing at the wafer level to ensure the circuitry's functionality and performance. This critical process requires maintaining extremely low temperatures, typically below 5 Kelvin, for both the wafer and the delicate testing probes. The ability to reliably characterize these advanced circuits in their operational cryogenic environment is fundamental for their successful fabrication and integration into next-generation technologies. Current approaches face significant hurdles in achieving these conditions. A primary challenge involves simultaneously cooling the wafer and probes to the required cryogenic temperatures while preserving a flat wafer geometry for consistent probe contact. Conventional wafer-holding techniques, such as gas pressure or electrostatic attraction, are ineffective in vacuum or cryogenic conditions. Furthermore, applying compressive force from the wafer's front side risks damaging the circuitry, causes wafer bending, and provides inadequate heat sinking, particularly for the wafer's interior because of poor in-plane thermal conductance. Applying such force can lead to either wafer fracture from excessive force or poor thermal contact from insufficient force.

Technology Description

This technology provides a comprehensive system for wafer-level testing of superconducting and low-temperature circuitry, operating below 5 Kelvin. It features a two-chamber vacuum architecture with actively and passively cooled heat shields, and an inner chamber constructed from high-purity, high-thermal-conductivity metals. A novel two-part wafer-holding structure includes a removable wafer carrier, designed with materials matching the wafer's thermal expansion, and a fixed chuck for precise force application and alignment. A key component is a passive helium convection loop, utilizing an evaporator integrated into the chuck and a condenser on the cryocooler, connected by flexible bellows, to ensure efficient heat transfer. The system also incorporates a load lock for wafer insertion without breaking vacuum and a precise mechanical positioning stage.

This technology is highly differentiated by effectively overcoming significant challenges in cryogenic wafer testing. Unlike conventional methods that struggle with maintaining wafer flatness, uniform cooling, and reliable thermal contact in vacuum, this system employs a unique two-part wafer holder that minimizes thermal stresses and ensures stable geometry. The passive helium convection loop offers superior thermal conductance, mechanical compliance, and reduced vibration compared to traditional thermal straps, crucial for sensitive cryogenic environments. Furthermore, the integrated load lock enables high-throughput, automated testing by allowing wafer exchange without compromising the main chamber's vacuum, leading to more reliable and efficient characterization of advanced low-temperature circuits.