SOI wafer selection for CCD/SOI-CMOS technology [Abstract]
October 2, 2000
2000 IEEE Int. SOI Conf. Proc., 2-5 October 2000, pp. 136-137.
We have developed a process that monolithically integrates fully depleted SOI CMOS (FDSOI) with high-performance CCD image sensors. This integrated technology that enables charged-coupled devices (CCD's) to be in close proximity to, yet isolated from, FDSOI circuits. This approach exploits both the advantages of FDSOI (fast, low-power CMOS with potentially enhanced radiation performance) and those of CCD's (high quantum efftciency, low noise, and architectural flexibility). This 3.3 V, 0.3 mu m CCD/FDSOI-CMOS technology thus enables fabrication of low-power, compact imaging systems. Material requirements for CCD imagers are perhaps the most stringent of any device and require special attention to the quality of the bulk or handle wafer. We report here characterization of various SOI handle wafers for use in fabrication of bulk imaging devices.