Publications

Refine Results

(Filters Applied) Clear All

Chip-scale molecular clock

Published in:
IEEE J. Solid-State Circuits, Vol. 54, No. 4, April 2019, pp. 914-26.

Summary

An ultra-stable time-keeping device is presented, which locks its output clock frequency to the rotational-mode transition of polar gaseous molecules. Based on a high-precision spectrometer in the sub-terahertz (THz) range, our new clocking scheme realizes not only fully electronic operation but also implementations using mainstream CMOS technology. Meanwhile, the small wavelength of probing wave and high absorption intensity of our adopted molecules (carbonyl sulfide, 16O12C32S) also enable miniaturization of the gas cell. All these result in an "atomic-clock-grade" frequency reference with small size, power, and cost. This paper provides the architectural and chip-design details of the first proof-of-concept molecular clock using a 65-nm CMOS bulk technology. Using a 231.061-GHz phase-locked loop (PLL) with frequency-shift keying (FSK) modulation and a sub-THz FET detector with integrated lock-in function, the chip probes the accurate transition frequency of carbonyl sulfide (OCS) gas inside a single-mode waveguide, and accordingly adjusts the 80-MHz output of a crystal oscillator. The clock consumes only 66 mW of dc power and has a measured Allan deviation of 3.8 × 10^−10 at an averaging time of tau = 1000 s.
READ LESS

Summary

An ultra-stable time-keeping device is presented, which locks its output clock frequency to the rotational-mode transition of polar gaseous molecules. Based on a high-precision spectrometer in the sub-terahertz (THz) range, our new clocking scheme realizes not only fully electronic operation but also implementations using mainstream CMOS technology. Meanwhile, the small...

READ MORE

High-resolution, high-throughput, CMOS-compatible electron beam patterning

Published in:
SPIE Advanced Lithography, 26 February - 2 March 2017.

Summary

Two scanning electron beam lithography (SEBL) patterning processes have been developed, one positive and one negative tone. The processes feature nanometer-scale resolution, chemical amplification for faster throughput, long film life under vacuum, and sufficient etch resistance to enable patterning of a variety of materials with a metal-free (CMOS/MEMS compatible) tool set. These resist processes were developed to address two limitations of conventional SEBL resist processes: (1) low areal throughput and (2) limited compatibility with the traditional microfabrication infrastructure.
READ LESS

Summary

Two scanning electron beam lithography (SEBL) patterning processes have been developed, one positive and one negative tone. The processes feature nanometer-scale resolution, chemical amplification for faster throughput, long film life under vacuum, and sufficient etch resistance to enable patterning of a variety of materials with a metal-free (CMOS/MEMS compatible) tool...

READ MORE

Enhancing the far-ultraviolet sensitivity of silicon complementary metal oxide semiconductor imaging arrays

Summary

We report our progress toward optimizing backside-illuminated silicon P-type intrinsic N-type complementary metal oxide semiconductor devices developed by Teledyne Imaging Sensors (TIS) for far-ultraviolet (UV) planetary science applications. This project was motivated by initial measurements at Southwest Research Institute of the far-UV responsivity of backside-illuminated silicon PIN photodiode test structures, which revealed a promising QE in the 100 to 200 nm range. Our effort to advance the capabilities of thinned silicon wafers capitalizes on recent innovations in molecular beam epitaxy (MBE) doping processes. Key achievements to date include the following: (1) representative silicon test wafers were fabricated by TIS, and set up for MBE processing at MIT Lincoln Laboratory; (2) preliminary far-UV detector QE simulation runs were completed to aid MBE layer design; (3) detector fabrication was completed through the pre-MBE step; and (4) initial testing of the MBE doping process was performed on monitoring wafers, with detailed quality assessments.
READ LESS

Summary

We report our progress toward optimizing backside-illuminated silicon P-type intrinsic N-type complementary metal oxide semiconductor devices developed by Teledyne Imaging Sensors (TIS) for far-ultraviolet (UV) planetary science applications. This project was motivated by initial measurements at Southwest Research Institute of the far-UV responsivity of backside-illuminated silicon PIN photodiode test structures...

READ MORE

Digital pixel CMOS focal plane array with on-chip multiply accumulate units for low-latency image processing

Published in:
SPIE, Vol. 9070, Infrared Technology and Applications XL, 5 May 2014, 90703B.

Summary

A digital pixel CMOS focal plane array has been developed to enable low latency implementations of image processing systems such as centroid trackers, Shack-Hartman wavefront sensors, and Fitts correlation trackers through the use of in-pixel digital signal processing (DSP) and generic parallel pipelined multiply accumulate (MAC) units. Light intensity digitization occurs at the pixel level, enabling in-pixel DSP and noiseless data transfer from the pixel array to the peripheral processing units. The pipelined processing of row and column image data prior to off chip readout reduces the required output bandwidth of the image sensor, thus reducing the latency of computations necessary to implement various image processing systems. Data volume reductions of over 80% lead to sub 10us latency for completing various tracking and sensor algorithms. This paper details the architecture of the pixel-processing imager (PPI) and presents some initial results from a prototype device fabricated in a standard 65nm CMOS process hybridized to a commercial off-the-shelf short-wave infrared (SWIR) detector array.
READ LESS

Summary

A digital pixel CMOS focal plane array has been developed to enable low latency implementations of image processing systems such as centroid trackers, Shack-Hartman wavefront sensors, and Fitts correlation trackers through the use of in-pixel digital signal processing (DSP) and generic parallel pipelined multiply accumulate (MAC) units. Light intensity digitization...

READ MORE

Single event transients in digital CMOS - a review

Published in:
IEEE Trans. Nucl. Sci., Vol. 60, No. 3, June 2013, pp. 1767-90.

Summary

The creation of soft errors due to the propagation of single event transients (SETs) is a significant reliability challenge in modern CMOS logic. SET concerns continue to be exacerbated by Moore's Law technology scaling. This paper presents a review of digital single event transient research, including: a brief historical overview of the emergence of SET phenomena, a review of the present understanding of SET mechanisms, a review of the state-of-the-art in SET testing and modelling, a discussion of mitigation techniques, and a discussion of the impact of technology scaling trends on future SET significance.
READ LESS

Summary

The creation of soft errors due to the propagation of single event transients (SETs) is a significant reliability challenge in modern CMOS logic. SET concerns continue to be exacerbated by Moore's Law technology scaling. This paper presents a review of digital single event transient research, including: a brief historical overview...

READ MORE

Improvement of SOI MOSFET RF performance by implant optimization

Published in:
IEEE Microw. Wirel. Compon. Lett., Vol. 20, No. 5, May 2010, pp. 271-273.

Summary

The characteristics of silicon on insulator MOSFETs are modified to enhance the RF performance by varying channel implants. Without adding new masks or fabrication steps to the standard CMOS process, this approach can be easily applied in standard foundry fabrication. The transconductance, output resistance, and breakdown voltage can be increased by eliminating channel and drain extension implants. As a result, the fmax of the modified n-MOSFET with a 150 nm gate length exceeds 120 GHz, showing a 20% improvement over the standard MOSFET for digital circuits on the same wafer.
READ LESS

Summary

The characteristics of silicon on insulator MOSFETs are modified to enhance the RF performance by varying channel implants. Without adding new masks or fabrication steps to the standard CMOS process, this approach can be easily applied in standard foundry fabrication. The transconductance, output resistance, and breakdown voltage can be increased...

READ MORE

Effects of ionizing radiation on digital single event transients in a 180-nm fully depleted SOI process

Published in:
2009 IEEE Nuclear & Space Radiation Effects Conf., 07/20/2009 [in: IEEE Trans. Nuclear Sci., Vol. 56, No. 9, December 2009, pp. 3477-3482].

Summary

Effects of ionizing radiation on single event transients are reported for Fully Depleted SOI (FDSOI) technology using experiments and simulations. Logic circuits, i.e. CMOS inverter chains, were irradiated with cobalt-60 gamma radiation. When charge is induced in the n-channel FET with laser-probing techniques, laser-induced transients widen with increased total dose. This is because radiation causes charge to be trapped in the buried oxide, and reduces the p-channel FET drive current. When the p-channel FET drive current is reduced, the time required to restore the output of the laser-probed FET back to its original condition is increased, i.e. the upset transient width is increased. A widening of the transient pulse is also observed when a positive bias is applied to the wafer without any exposure to radiation. This is because a positive wafer bias reproduces the shifts inFET threshold voltages that occur during total dose irradiation. Results were also verified with heavy ion testing and mixed mode simulations.
READ LESS

Summary

Effects of ionizing radiation on single event transients are reported for Fully Depleted SOI (FDSOI) technology using experiments and simulations. Logic circuits, i.e. CMOS inverter chains, were irradiated with cobalt-60 gamma radiation. When charge is induced in the n-channel FET with laser-probing techniques, laser-induced transients widen with increased total dose...

READ MORE

Channel engineering of SOI MOSFETs for RF applications

Summary

Channel engineering of SOI MOSFETs is explored by altering ion implantation without adding any new fabrication steps to the standard CMOS process. The effects of implantation on characteristics important for RF applications, such as transconductance, output resistance, breakdown voltage, are compared. Data show that the best overall RF MOSFET has no body and drain-extension implants.
READ LESS

Summary

Channel engineering of SOI MOSFETs is explored by altering ion implantation without adding any new fabrication steps to the standard CMOS process. The effects of implantation on characteristics important for RF applications, such as transconductance, output resistance, breakdown voltage, are compared. Data show that the best overall RF MOSFET has...

READ MORE

High density plasma etching of titanium nitride metal gate electrodes for fully depleted silicon-on-insulator subthreshold transistor integration

Published in:
J. Vacuum Sci. Technol. B, Microelectron. Process. Phenon., Vol. 27, No. 6, p. 2472-2479.

Summary

Etching of TiN metal gate materials as a part of an integrated flow to fabricate fully depleted silicon-on-insulator ultralow-power transistors is reported. TiN etching is characterized as a function of source power, bias power, gas composition, and substrate temperature in a high density inductively coupled plasma reactor. Under the conditions used in this work, the TiN etch rate appears to be ion flux limited and exhibits a low ion enhanced etching activation energy of 0.033 eV. Notching of the polysilicon layer above the TiN may occur during the polysilicon overetch step as well as the TiN overetch step. Notching is not significantly affected by charging of the underlying gate dielectric under the conditions used. By optimizing the plasma etch process conditions, TiN:SiO2 selectivity of nearly 1000:1 is achieved, and a two-step TiN main etch and TiN overetch process yields well-defined metal gate structures without severe gate profile artifacts.
READ LESS

Summary

Etching of TiN metal gate materials as a part of an integrated flow to fabricate fully depleted silicon-on-insulator ultralow-power transistors is reported. TiN etching is characterized as a function of source power, bias power, gas composition, and substrate temperature in a high density inductively coupled plasma reactor. Under the conditions...

READ MORE

A 4-side tileable back illuminated 3D-integrated Mpixel CMOS image sensor

Summary

The dominant trend with conventional image sensors is toward scaled-down pixel sizes to increase spatial resolution and decrease chip size and cost. While highly capable chips, these monolithic image sensors devote substantial perimeter area to signal acquisition and control circuitry and trade off pixel complexity for fill factor. For applications such as wide-area persistent surveillance, reconnaissance, and astronomical sky surveys it is desirable to have simultaneous near-real-time imagery with fast, wide field-of-view coverage. Since the fabrication of a complex large-format sensor on a single piece of silicon is cost and yield-prohibitive and is limited to the wafer size, for these applications many smaller-sized image sensors are tiled together to realize very large arrays. Ideally the tiled image sensor has no missing pixels and the pixel pitch is continuous across the seam to minimize loss of information content. CCD-based imagers have been favored for these large mosaic arrays because of their low noise and high sensitivity, but CMOS-based image sensors bring architectural benefits, including electronic shutters, enhanced radiation tolerance, and higher data-rate digital outputs that are more easily scalable to larger arrays. In this report the first back-illuminated, 1 Mpixel, 3D-integrated CMOS image sensor with 8 mum-pitch 3D via connections. The chip employs a conventional pixel layout and requires 500 mum of perimeter silicon to house the support circuitry and protect the array from saw damage. In this paper we present a back-illuminated 1 Mpixel CMOS image sensor tile that includes a 64-channel vertically integrated ADC chip stack, and requires only a few pixels of silicon perimeter to the pixel array. The tile and system connector design support 4-side abuttability and fast burst data rates.
READ LESS

Summary

The dominant trend with conventional image sensors is toward scaled-down pixel sizes to increase spatial resolution and decrease chip size and cost. While highly capable chips, these monolithic image sensors devote substantial perimeter area to signal acquisition and control circuitry and trade off pixel complexity for fill factor. For applications...

READ MORE