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Energy efficiency benefits of subthreshold-optimized transistors for digital logic

Published in:
2014 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conf. (S3S), 6-9 October 2014.

Summary

The minimum energy point of an integrated circuit (IC) is defined as the value of the supply voltage at which the energy per operation of the circuit is minimized. Several factors influence what the value of this voltage can be, including the topology of the circuit itself, the input activity factor, and the process technology in which the circuit is implemented. For application-specific ICs (ASICs), the minimum energy point usually occurs at a subthreshold supply voltage. Advances in subthreshold circuit design now permit correct circuit operation at, or even below, the minimum energy point. Since energy consumption is proportional to the square of the supply voltage, circuit design techniques and process technology choices that reduce the minimum energy point inherently improve the energy efficiency of ICs. Previous research has shown that optimizing process technology for subthreshold operation can improve IC energy efficiency. This, coupled with the energy efficiency advantages offered by fully-depleted silicon-on-insulator (FDSOI) processes, have led to the development of a subthreshold-optimized FDSOI process at MIT Lincoln Laboratory (MITLL) called xLP (Extreme Low Power). However, to date there has not been a quantitative estimate of the energy efficiency benefit of xLP or other analagous technology for complex digital circuits. This paper will show via simulation that the xLP process technology enables energy efficiency improvements that exceed that of process scaling by one generation. Specifically, the process is shown to improve power delay product by 57% vs. the IBM 90nm low power bulk process, and by 9% vs. the IBM 65 nm low power bulk technology at 0.3V.
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Summary

The minimum energy point of an integrated circuit (IC) is defined as the value of the supply voltage at which the energy per operation of the circuit is minimized. Several factors influence what the value of this voltage can be, including the topology of the circuit itself, the input activity...

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Radiation effects in 3D integrated SOI SRAM circuits

Summary

Radiation effects are presented for the first time for vertically integrated 3 x 64 -kb SOI SRAM circuits fabricated using the 3D process developed at MIT Lincoln Laboratory. Three fully-fabricated 2D circuit wafers are stacked using standard CMOS fabrication techniques including thin-film planarization, layer alignment and oxide bonding. Micron-scale dense 3D vias are fabricated to interconnect circuits between tiers. Ionizing dose and single event effects are discussed for proton irradiation with energies between 4.8 and 500 MeV. Results are compared with 14-MeV neutron irradiation. Single event upset cross section, tier-to-tier and angular effects are discussed. The interaction of 500-MeV protons with tungsten interconnects is investigated usingMonte-Carlo simulations. Results show no tier-to-tier effects and comparable radiation effects on 2D and 3D SRAMs. 3DIC technology should be a good candidate for fabricating circuits for space applications.
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Summary

Radiation effects are presented for the first time for vertically integrated 3 x 64 -kb SOI SRAM circuits fabricated using the 3D process developed at MIT Lincoln Laboratory. Three fully-fabricated 2D circuit wafers are stacked using standard CMOS fabrication techniques including thin-film planarization, layer alignment and oxide bonding. Micron-scale dense...

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SET characterization in logic circuits fabricated in a 3DIC technology

Summary

Single event transients are characterized for the first time in logic gate circuits fabricated in a novel 3DIC technology where SET test circuits are vertically integrated on three tiers in a 20-um-thick layer. This 3D technology is extremely will suited for high-density circuit integration because of the small dimension the tier-to-tier circuit interconnects, which are 1.25-um-wide-through-oxide-vias. Transient pulse width distributions were characterized simultaneously on each tier during exposure to krypton heavy ions. The difference in SET pulse width and cross-section among the three tiers is discussed. Experimental test results are explaine dby considering the electrical characteristics of the FETs on the 2D wafers before 3D integration, and by considering the energy deposited by the Kr ions passing through the various material laters of the 3DIC stack. We also show that the backmetal layer available on the upper tiers can be used to tune independently the nFET and pFET current drive, and change the SET pulse width and cross-section. This 3DIC technology appears to be a good candidate for space applications.
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Summary

Single event transients are characterized for the first time in logic gate circuits fabricated in a novel 3DIC technology where SET test circuits are vertically integrated on three tiers in a 20-um-thick layer. This 3D technology is extremely will suited for high-density circuit integration because of the small dimension the...

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FDSOI process technology for subthreshold-operation ultra-low power electronics

Published in:
ECS Meeting, 1 May 2011 (in: Adv. Semiconductor-on-Insulator Technol. Rel. Phys., Vol. 35, No. 5, 2011, pp. 179-188).
Topic:

Summary

Ultralow-power electronics will expand the technological capability of handheld and wireless devices by dramatically improving battery life and portability. In addition to innovative low-power design techniques, a complementary process technology is required to enable the highest performance devices possible while maintaining extremely low power consumption. Transistors optimized for subthreshold operation at 0.3 V may achieve a 97% reduction in switching energy compared to conventional transistors. The process technology described in this article takes advantage of the capacitance and performance benefits of thin-body silicon-on-insulator devices, combined with a workfunction engineered mid-gap metal gate.
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Summary

Ultralow-power electronics will expand the technological capability of handheld and wireless devices by dramatically improving battery life and portability. In addition to innovative low-power design techniques, a complementary process technology is required to enable the highest performance devices possible while maintaining extremely low power consumption. Transistors optimized for subthreshold operation...

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Work-function-tuned TiN metal gate FDSOI transistors for subthreshold operation

Published in:
IEEE Trans. Electron Devices, Vol. 58, No. 2, February 2011, pp. 419-426.

Summary

The effective work function of a reactively sputtered TiN metal gate is shown to be tunable from 4.30 to 4.65 eV. The effective work function decreases with nitrogen flow during reactive sputter deposition. Nitrogen annealing increases the effective work function and reduces Dit. Thinner TiN improves the variation in effective work function and reduces gate dielectric charge. Doping of the polysilicon above the TiN metal gate with B or P has negligible effect on the effective work function. The work-function-tuned TiN is integrated into ultralow-power fully depleted silicon-on-insulator CMOS transistors optimized for subthreshold operation at 0.3 V. The following performance metrics are achieved: 64-80-mV/dec subthreshold swing, PMOS/NMOS on-current ratio near 1, 71% reduction inCgd, and 55% reduction in Vt variation when compared with conventional transistors, although significant short-channel effects are observed.
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Summary

The effective work function of a reactively sputtered TiN metal gate is shown to be tunable from 4.30 to 4.65 eV. The effective work function decreases with nitrogen flow during reactive sputter deposition. Nitrogen annealing increases the effective work function and reduces Dit. Thinner TiN improves the variation in effective...

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Improvement of SOI MOSFET RF performance by implant optimization

Published in:
IEEE Microw. Wirel. Compon. Lett., Vol. 20, No. 5, May 2010, pp. 271-273.

Summary

The characteristics of silicon on insulator MOSFETs are modified to enhance the RF performance by varying channel implants. Without adding new masks or fabrication steps to the standard CMOS process, this approach can be easily applied in standard foundry fabrication. The transconductance, output resistance, and breakdown voltage can be increased by eliminating channel and drain extension implants. As a result, the fmax of the modified n-MOSFET with a 150 nm gate length exceeds 120 GHz, showing a 20% improvement over the standard MOSFET for digital circuits on the same wafer.
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Summary

The characteristics of silicon on insulator MOSFETs are modified to enhance the RF performance by varying channel implants. Without adding new masks or fabrication steps to the standard CMOS process, this approach can be easily applied in standard foundry fabrication. The transconductance, output resistance, and breakdown voltage can be increased...

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FDSOI process technology for subthreshold-operation ultralow-power electronics

Published in:
Proc. of the IEEE, Vol. 98, No. 2, February 2010, pp. 333-342.
Topic:

Summary

Ultralow-power electronics will expand the technological capability of handheld and wireless devices by dramatically improving battery life and portability. In addition to innovative low-power design techniques, a complementary process technology is required to enable the highest performance devices possible while maintaining extremely low power consumption. Transistors optimized for subthreshold operation at 0.3 V may achieve a 97% reduction in switching energy compared to conventional transistors. The process technology described in this article takes advantage of the capacitance and performance benefits of thin-body silicon-oninsulator devices, combined with a workfunction engineered mid-gap metal gate.
READ LESS

Summary

Ultralow-power electronics will expand the technological capability of handheld and wireless devices by dramatically improving battery life and portability. In addition to innovative low-power design techniques, a complementary process technology is required to enable the highest performance devices possible while maintaining extremely low power consumption. Transistors optimized for subthreshold operation...

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Effects of ionizing radiation on digital single event transients in a 180-nm fully depleted SOI process

Published in:
2009 IEEE Nuclear & Space Radiation Effects Conf., 07/20/2009 [in: IEEE Trans. Nuclear Sci., Vol. 56, No. 9, December 2009, pp. 3477-3482].

Summary

Effects of ionizing radiation on single event transients are reported for Fully Depleted SOI (FDSOI) technology using experiments and simulations. Logic circuits, i.e. CMOS inverter chains, were irradiated with cobalt-60 gamma radiation. When charge is induced in the n-channel FET with laser-probing techniques, laser-induced transients widen with increased total dose. This is because radiation causes charge to be trapped in the buried oxide, and reduces the p-channel FET drive current. When the p-channel FET drive current is reduced, the time required to restore the output of the laser-probed FET back to its original condition is increased, i.e. the upset transient width is increased. A widening of the transient pulse is also observed when a positive bias is applied to the wafer without any exposure to radiation. This is because a positive wafer bias reproduces the shifts inFET threshold voltages that occur during total dose irradiation. Results were also verified with heavy ion testing and mixed mode simulations.
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Summary

Effects of ionizing radiation on single event transients are reported for Fully Depleted SOI (FDSOI) technology using experiments and simulations. Logic circuits, i.e. CMOS inverter chains, were irradiated with cobalt-60 gamma radiation. When charge is induced in the n-channel FET with laser-probing techniques, laser-induced transients widen with increased total dose...

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Three-dimensional integration technology for advanced focal planes

Summary

We have developed a three-dimensional (3D) circuit integration technology that exploits the advantages of silicon-on-insulator (SOI) technology to enable wafer-level stacking and micrometer-scale electrical interconnection of fully fabricated circuit wafers. This paper describes the 3D technology and discusses some of the advanced focal plane arrays that have been built using it.
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Summary

We have developed a three-dimensional (3D) circuit integration technology that exploits the advantages of silicon-on-insulator (SOI) technology to enable wafer-level stacking and micrometer-scale electrical interconnection of fully fabricated circuit wafers. This paper describes the 3D technology and discusses some of the advanced focal plane arrays that have been built using...

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Channel engineering of SOI MOSFETs for RF applications

Summary

Channel engineering of SOI MOSFETs is explored by altering ion implantation without adding any new fabrication steps to the standard CMOS process. The effects of implantation on characteristics important for RF applications, such as transconductance, output resistance, breakdown voltage, are compared. Data show that the best overall RF MOSFET has no body and drain-extension implants.
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Summary

Channel engineering of SOI MOSFETs is explored by altering ion implantation without adding any new fabrication steps to the standard CMOS process. The effects of implantation on characteristics important for RF applications, such as transconductance, output resistance, breakdown voltage, are compared. Data show that the best overall RF MOSFET has...

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