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Moving clutter spectral filter for Terminal Doppler Weather Radar

Author:
Published in:
34th Conf. on Radar Meteorology, 5-9 October 2009.

Summary

Detecting low-altitude wind shear in support of aviation safety and efficiency is the primary mission of the Terminal Doppler Weather Radar (TDWR). The wind-shear detection performance depends directly on the quality of the data produced by the TDWR. At times the data quality suffers from the presence of clutter. Al-though stationary ground clutter signals can be removed by a high-pass filter, moving clutter such as birds and roadway traffic cannot be attenuated using the same technique because their signal power can exist any-where in the Doppler velocity spectrum. Furthermore, because the TDWR is a single-polarization radar, polarimetry cannot be used to discriminate these types of clutter from atmospheric signals. The moving clutter problem is exacerbated at Western sites with dry microbursts, because their low signal-to-noise ratios (SNRs) are more easily masked by un-wanted moving clutter. For Las Vegas (LAS), Nevada, the offending clutter is traffic on roads that are oriented along the radar line of sight near the airport. The radar is located at a significantly higher altitude than the town, improving the visibility to the roads, and giving LAS the worst road clutter problem of all TDWR sites. The Salt Lake City (SLC), Utah, airport is located near the Great Salt Lake, which is the biggest inland staging area for migrating seabirds in the country. It, therefore, suffers from bird clutter, which not only can obscure wind shear signatures but can also mimic them to trigger false alarms. The TDWR "dry" site issues are discussed in more detail by Cho (2008). In order to mitigate these problems, we developed a moving clutter spectral filter (MCSF). In this paper we describe the algorithm and present preliminary test results.
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Summary

Detecting low-altitude wind shear in support of aviation safety and efficiency is the primary mission of the Terminal Doppler Weather Radar (TDWR). The wind-shear detection performance depends directly on the quality of the data produced by the TDWR. At times the data quality suffers from the presence of clutter. Al-though...

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A log-frequency approach to the identification of the Wiener-Hammerstein model

Published in:
IEEE Sig. Proc. Lett., Vol. 16, No. 10, October 2009, pp. 889-892.

Summary

In this paper we present a simple closed-form solution to the Wiener-Hammerstein (W-H) identification problem. The identification process occurs in the log-frequency domain where magnitudes and phases are separable. We show that the theoretically optimal W-H identification is unique up to an amplitude, phase and delay ambiguity, and that the nonlinearity enables the separate identification of the individual linear time invariant (LTI) components in a W-H architecture.
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Summary

In this paper we present a simple closed-form solution to the Wiener-Hammerstein (W-H) identification problem. The identification process occurs in the log-frequency domain where magnitudes and phases are separable. We show that the theoretically optimal W-H identification is unique up to an amplitude, phase and delay ambiguity, and that the...

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2-D processing of speech for multi-pitch analysis.

Published in:
INTERSPEECH 2009, 6-10 September 2009.

Summary

This paper introduces a two-dimensional (2-D) processing approach for the analysis of multi-pitch speech sounds. Our framework invokes the short-space 2-D Fourier transform magnitude of a narrowband spectrogram, mapping harmonically related signal components to multiple concentrated entities in a new 2-D space. First, localized time-frequency regions of the spectrogram are analyzed to extract pitch candidates. These candidates are then combined across multiple regions for obtaining separate pitch estimates of each speech-signal component at a single point in time. We refer to this as multi-region analysis (MRA). By explicitly accounting for pitch dynamics within localized time segments, this separability is distinct from that which can be obtained using short-time autocorrelation methods typically employed in state-of-the-art multi-pitch tracking algorithms. We illustrate the feasibility of MRA for multi-pitch estimation on mixtures of synthetic and real speech.
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Summary

This paper introduces a two-dimensional (2-D) processing approach for the analysis of multi-pitch speech sounds. Our framework invokes the short-space 2-D Fourier transform magnitude of a narrowband spectrogram, mapping harmonically related signal components to multiple concentrated entities in a new 2-D space. First, localized time-frequency regions of the spectrogram are...

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Large-scale analysis of formant frequency estimation variability in conversational telephone speech

Published in:
INTERSPEECH 2009, 6-10 September 2009.

Summary

We quantify how the telephone channel and regional dialect influence formant estimates extracted from Wavesurfer in spontaneous conversational speech from over 3,600 native American English speakers. To the best of our knowledge, this is the largest scale study on this topic. We found that F1 estimates are higher in cellular channels than those in landline, while F2 in general shows an opposite trend. We also characterized vowel shift trends in northern states in U.S.A. and compared them with the Northern city chain shift (NCCS). Our analysis is useful in forensic applications where it is important to distinguish between speaker, dialect, and channel characteristics.
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Summary

We quantify how the telephone channel and regional dialect influence formant estimates extracted from Wavesurfer in spontaneous conversational speech from over 3,600 native American English speakers. To the best of our knowledge, this is the largest scale study on this topic. We found that F1 estimates are higher in cellular...

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Compressed sensing arrays for frequency-sparse signal detection and geolocation

Published in:
Proc. of the 2009 DoD High Performance Computing Modernization Program Users Group Conf., HPCMP-UGC, 15 June 2009, pp. 297-301.

Summary

Compressed sensing (CS) can be used to monitor very wide bands when the received signals are sparse in some basis. We have developed a compressed sensing receiver architecture with the ability to detect, demodulate, and geolocate signals that are sparse in frequency. In this paper, we evaluate detection, reconstruction, and angle of arrival (AoA) estimation via Monte Carlo simulation and find that, using a linear 4- sensor array and undersampling by a factor of 8, we achieve near-perfect detection when the received signals occupy up to 5% of the bandwidth being monitored and have an SNR of 20 dB or higher. The signals in our band of interest include frequency-hopping signals detected due to consistent AoA. We compare CS array performance using sensor-frequency and space-frequency bases, and determine that using the sensor-frequency basis is more practical for monitoring wide bands. Though it requires that the received signals be sparse in frequency, the sensor-frequency basis still provides spatial information and is not affected by correlation between uncompressed basis vectors.
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Summary

Compressed sensing (CS) can be used to monitor very wide bands when the received signals are sparse in some basis. We have developed a compressed sensing receiver architecture with the ability to detect, demodulate, and geolocate signals that are sparse in frequency. In this paper, we evaluate detection, reconstruction, and...

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Polyphase nonlinear equalization of time-interleaved analog-to-digital converters

Published in:
IEEE J. Sel. Top. Sig. Process., Vol. 3, No. 3, June 2009, pp. 362-373.

Summary

As the demand for higher data rates increases, commercial analog-to-digital converters (ADCs) are more commonly being implemented with multiple on-chip converters whose outputs are time-interleaved. The distortion generated by time-interleaved ADCs is now not only a function of the nonlinear behavior of the constituent circuitry, but also mismatches associated with interleaving multiple output streams. To mitigate distortion generated by time-interleaved ADCs, we have developed a polyphase NonLinear EQualizer (pNLEQ) which is capable of simultaneously mitigating distortion generated by both the on-chip circuitry and mismatches due to time interleaving. In this paper, we describe the pNLEQ architecture and present measurements of its performance.
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Summary

As the demand for higher data rates increases, commercial analog-to-digital converters (ADCs) are more commonly being implemented with multiple on-chip converters whose outputs are time-interleaved. The distortion generated by time-interleaved ADCs is now not only a function of the nonlinear behavior of the constituent circuitry, but also mismatches associated with...

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Extending the dynamic range of RF receivers using nonlinear equalization

Summary

Systems currently being developed to operate across wide bandwidths with high sensitivity requirements are limited by the inherent dynamic range of a receiver's analog and mixed-signal components. To increase a receiver's overall linearity, we have developed a digital NonLinear EQualization (NLEQ) processor which is capable of extending a receiver's dynamic range from one to three orders of magnitude. In this paper we describe the NLEQ architecture and present measurements of its performance.
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Summary

Systems currently being developed to operate across wide bandwidths with high sensitivity requirements are limited by the inherent dynamic range of a receiver's analog and mixed-signal components. To increase a receiver's overall linearity, we have developed a digital NonLinear EQualization (NLEQ) processor which is capable of extending a receiver's dynamic...

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A polyphase nonlinear equalization architecture and semi-blind identification method

Published in:
42th Asilomar Conf. on Signals, Systems, and Computers, 27 October 2008, pp. 593-597.

Summary

In this paper, we present an architecture and semiblind identification method for a polyphase nonlinear equalizer (pNLEQ). Such an equalizer is useful for extending the dynamic range of time-interleaved analog-to-digital converters (ADCs). Our proposed architecture is a polyphase extension to other architectures that partition the Volterra kernel into small nonlinear filters with relatively low computational complexity. Our semi-blind identification technique addresses important practical concerns in the equalizer identification process. We describe our architecture and demonstrate its performance with measured results when applied to a National Semiconductor ADC081000.
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Summary

In this paper, we present an architecture and semiblind identification method for a polyphase nonlinear equalizer (pNLEQ). Such an equalizer is useful for extending the dynamic range of time-interleaved analog-to-digital converters (ADCs). Our proposed architecture is a polyphase extension to other architectures that partition the Volterra kernel into small nonlinear...

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The cube coefficient subspace architecture for nonlinear digital predistortion

Published in:
42th Asilomar Conf. on Signals, Systems, and Computers, 27 October 2008, pp. 1857-1861.

Summary

In this paper, we present the cube coefficient subspace (CCS) architecture for linearizing power amplifiers (PAs), which divides the overparametrized Volterra kernel into small, computationally efficient subkernels spanning only the portions of the full multidimensional coefficient space with the greatest impact on linearization. Using measured results from a Q-Band solid state PA, we demonstrate that the CCS predistorter architecture achieves better linearization performance than state-of-the-art memory polynomials and generalized memory polynomials.
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Summary

In this paper, we present the cube coefficient subspace (CCS) architecture for linearizing power amplifiers (PAs), which divides the overparametrized Volterra kernel into small, computationally efficient subkernels spanning only the portions of the full multidimensional coefficient space with the greatest impact on linearization. Using measured results from a Q-Band solid...

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PVTOL: providing productivity, performance, and portability to DoD signal processing applications on multicore processors

Published in:
DoD HPCMP 2008, High Performance Computing Modernization Program Users Group Conf., 14 July 2008, pp. 327-333.

Summary

PVTOL provides an object-oriented C++ API that hides the complexity of multicore architectures within a PGAS programming model, improving programmer productivity. Tasks and conduits enable data flow patterns such as pipelining and round-robining. Hierarchical maps concisely describe how to allocate hierarchical arrays across processor and memory hierarchies and provide a simple API for moving data across these hierarchies. Functors encapsulate computational kernels; new functors can be easily developed using the PVTOL API and can be fused for more efficient computation. Existing computation and communication technologies that are optimized for various architectures are used to achieve high performance. PVTOL abstracts the details of the underlying processor architectures to provide portability. We are actively developing PVTOL for Intel, PowerPC and Cell architectures and intend to add support for more computational kernels on these architectures. FPGAs are becoming popular for accelerating computation in both the high performance computing (HPC) and high performance embedded computing (HPEC) communities. Integrated processor-FPGA technologies are now available from both HPC and HPEC vendors, e.g. Cray and Mercury Computer Systems. We plan to support FPGAs as co-processors in PVTOL. Finally, automated mapping technology has been demonstrated with pMatlab. We plan to begin implementing automated mapping in PVTOL next year. Similar to PVL, as PVTOL matures and is used in more projects at Lincoln, we plan to propose concepts demonstrated in PVTOL to HPEC-SI for adoption into future versions of VSIPL++.
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Summary

PVTOL provides an object-oriented C++ API that hides the complexity of multicore architectures within a PGAS programming model, improving programmer productivity. Tasks and conduits enable data flow patterns such as pipelining and round-robining. Hierarchical maps concisely describe how to allocate hierarchical arrays across processor and memory hierarchies and provide a...

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