We present an efficient architecture to perform on-chip nonlinear equalization of an anti-alias RF filter. The sparse polynomial equalizer (SPEq) achieves substantial power savings through co-design of the equalizer and the filter, which allows including the right number of processing elements, filter taps, and bits to maximize performance and minimize power consumption. The architecture was implemented in VHDL and fabricated in CMOS 65 nm technology. Testing results show that undesired spurs are suppressed to near the noise floor, improving the system's spur-free dynamic range by 25 dB in the median case, and consuming less than 12 mW of core power when operating at 200 MHz.