A compressed sensing analog-to-information converter with edge-triggered SAR ADC core
May 20, 2012
ISCAS 2012: IEEE Int. Symp. on Circuits and Systems, 20-23 May 2012, pp. 3162-3165.
This paper presents the design and implementation of an analog-to-information converter (AIC) based on compressed sensing. The core of the AIC is an edge-triggered charge-sharing SAR ADC. Compressed sensing is achieved through random sampling and asynchronous successive approximation conversion using the ADC core. Implemented in 90nm CMOS, the prototype SAR ADC core achieves a maximum sample rate of 9.5MS/s, an ENOB of 9.3 bits, and consumes 550 mu W from a 1.2V supply. Measurement results of the compressed sensing AIC demonstrate effective sub-Nyquist random sampling and reconstruction of signals with sparse frequency support suitable for wideband spectrum sensing applications. When accounting for the increased input bandwidth compared to Nyquist, the AIC achieves an effective FOM of 10.2fJ/conversion-step.