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Speech-state-adaptive simulation of co-channel talker interference suppression

Published in:
Proc. IEEE Int. Conf. on Acoustics, Speech and Signal Processing, ICASSP, 23-26 May 1989, pp. 361-364.

Summary

A co-channel talker interference suppression system processes an input waveform containing the sum of two simultaneous speech signals, referred to as the target and the jammer, to produce a waveform estimate of the target speech signal alone. This paper describes the evaluation of a simulated suppression system performing ideal suppression of a jammer signal given the voicing states (voiced, unvoiced, silent) of the target and jammer speech as a function of time and given the isolated target and jammer speech waveforms. By applying suppression to select regions of jammer speech as a function of the voicing states of the target and jammer, and by measuring the intelligibility of the resulting jammer suppressed co-channel speech, it is possible to identify those regions of co-channel speech on which interference suppression most improves intelligibility. Such results can help focus algorithm development efforts.
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Summary

A co-channel talker interference suppression system processes an input waveform containing the sum of two simultaneous speech signals, referred to as the target and the jammer, to produce a waveform estimate of the target speech signal alone. This paper describes the evaluation of a simulated suppression system performing ideal suppression...

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A block diagram compiler for a digital signal processing MIMD computer

Published in:
Proc. IEEE Int. Conf. on Acoustics, Speech and Signal Processing, ICASSP, Vol. 4, 6-9 April 1987, pp. 1867-1870.

Summary

A Block Diagram Compiler (BOC) has been designed and implemented for converting graphic block diagram descriptions of signal processing tasks into source code to be executed on a Multiple Instruction Stream - Multiple Data Stream (MIMD) array computer. The compiler takes as input a block diagram of a real-time DSP application, entered on a graphics CAE workstation, and translates it into efficient real-time assembly language code for the target multiprocessor array. The current implementation produces code for a rectangular grid of Texas Instruments TMS32010 signal processors built at Lincoln Laboratory, but the concept could be extended to other processors or other geometries in the same way that a good assembly language programmer would write it. This report begins by examining the current implementation of the BOC including relevant aspects of the target hardware. Next, we describe the task-assignment module, which uses a simulated annealing algorithm to assign the processing tasks of the DSP application to individual processors in the array. Finally, our experiences with the current version of the BOC software and hardware are reported.
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Summary

A Block Diagram Compiler (BOC) has been designed and implemented for converting graphic block diagram descriptions of signal processing tasks into source code to be executed on a Multiple Instruction Stream - Multiple Data Stream (MIMD) array computer. The compiler takes as input a block diagram of a real-time DSP...

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