SET characterization in logic circuits fabricated in a 3DIC technology
December 1, 2011
IEEE Trans. Nuclear Sci., Vol. 58, No. 6, December 2011, pp. 2555-2562.
Single event transients are characterized for the first time in logic gate circuits fabricated in a novel 3DIC technology where SET test circuits are vertically integrated on three tiers in a 20-um-thick layer. This 3D technology is extremely will suited for high-density circuit integration because of the small dimension the tier-to-tier circuit interconnects, which are 1.25-um-wide-through-oxide-vias. Transient pulse width distributions were characterized simultaneously on each tier during exposure to krypton heavy ions. The difference in SET pulse width and cross-section among the three tiers is discussed. Experimental test results are explaine dby considering the electrical characteristics of the FETs on the 2D wafers before 3D integration, and by considering the energy deposited by the Kr ions passing through the various material laters of the 3DIC stack. We also show that the backmetal layer available on the upper tiers can be used to tune independently the nFET and pFET current drive, and change the SET pulse width and cross-section. This 3DIC technology appears to be a good candidate for space applications.