Publications

A digital focal plane array (DFPA) architecture has been developed that incorporates per-pixel full-dynamic-range analog-to-digital conversion and orthogonal-transfer-based realtime digital signal processing capability. Several long-wave infrared-optimized pixel processing focal plane readout integrated circuit (ROIC) designs have been implemented, each accommodating a 256 x 256 30-um-pitch detector array. Demonstrated in this paper is the application of this DFPA ROIC architecture to problems of background pedestal mitigation, wide-field imaging, image stabilization, edge detection, and velocimetry. The DFPA architecture is reviewed, and pixel performance metrics are discussed in the context of the application examples. The measured data reported here are for DFPA ROICs implemented in 90-nm CMOS technology and hybridized to HgxCd1-xTe (MCT) detector arrays with cutoff wavelengths ranging from 7 to 14.5 m and a specified operating temperature of 60 K-80 K.

Although CMOS technology scaling has provided tremendous power and circuit density benefits for innumerable applications, focal plane array (FPA) readouts have largely been left behind due to dynamic range and signal-to-noise considerations. However, if an appropriate pixel front end can be constructed to interface with a mostly digital pixel, it is possible to develop sensor architectures for which performance scales favorably with advancing technology nodes. Although the front-end design must be optimized to interface with a particular detector, the dominant back end architecture provides considerable potential for design reuse. In this work, digitally dominated long wave infrared (LWIR) active pixel sensors with cutoff wavelengths between 9 and 14.5 um are demonstrated. Two ROIC designs are discussed, each fabricated in a 90-nm digital CMOS process and implementing a 256 x 256 pixel array on a 30-um pitch. In one of the implemented designs, the feasibility of implementing a 15-um pixel pitch FPA with a 500 million electron effective well depth, less than 0.5% non-linearity in the target range and a measured NEdT of less than 50 mK at f/4 and 60 K is demonstrated. Simple on-FPA signal processing allows for a much reduced readout bandwidth requirement with these architectures. To demonstrate the potential for commonality that is offered by a digitally dominated architecture, this LWIR sensor design is compared and contrasted with other digital focal plane architectures. Opportunities and challenges for application of this approach to various detector technologies, optical wavelength ranges and systems are discussed.

The digital focal plane array (DFPA) project demonstrates the enabling technologies necessary to build readout integrated circuits for very large infrared focal plane arrays (IR FPAs). Large and fast FPAs are needed for a new class of spectrally diverse sensors. Because of the requirement for high-resolution (low noise) sampling, and because of the sample rate needed for rapid acquisition of high-resolution spectra, it is highly desirable to perform analog-to-digital (A/D) conversion right at the pixel level. A dedicated A/D converter located under every pixel in a one-million-plus element array, and all-digital readout integrated circuits will enable multi- and hyper-spectral imaging systems with unprecedented spatial and spectral resolution and wide area coverage. DFPAs provide similar benefits to standard IR imaging systems as well. We have addressed the key enabling technologies for realizing the DFPA architecture in this work. Our effort concentrated on demonstrating a 60-micron footprint, 14-bit A/D converter and 2.5 Gbps, 16:1 digital multiplexer, the most basic components of the sensor. The silicon test chip was fabricated in a 0.18- micron CMOS process, and was designed to operate with HgxCd1-xTe detectors at cryogenic temperatures. Two A/D designs, one using static logic and one using dynamic logic, were built and tested for performance and power dissipation. Structures for evaluating the bit-error-rate of the multiplexer on-chip and through a differential output driver were implemented for a complete performance assessment. A unique IC probe card with fixtures to mount into an evacuated, closed-cycle helium dewar were also designed for testing up to 2.5 Gbps at temperatures as low as 50 K.

The effect of radiation on Hg(1-x)Cd(x)Te photodiodes is an important parameter to understand when determining the long-term performance limitations for the Cross-track Infrared Sounder (CrIS), a Fourier Transform interferometric sensor that will fly as part of the National Polar-orbiting Operational Enviornmental Satellite System (NPOESS). The CrIS sensor uses relatively large area photovoltaic detectors, 1mm in diameter. Each p-on-n Hg(1-x)Cd(x)Te photodiode consists of MBE grown, n-type material on lattice matched CdZnTe, with arsenic implantation used to form the junction. A 1mm diameter detector is achieved by using a lateral collection. Solar, and trapped protons are a significant source of radiation in the NPOESS 833 km orbits. We irradiated 22 LWIR detectors with protons at the Harvard Cyclotron Laboratory (HCL) and monitored the I-V performance and dynamic impedance of each detector. Three groups of detectors were irradiated with either 44, 99, 153-MeV protons, each between 1x10(10) - 4x10(12) p+/cm(2) (total range ~ 0.7 - 690 krad(Si)). Several I-V data sets were collected within that fluence range at all three energies. All the detectors were warmed to room temperature for approximately 96 hours following the largest proton dose, recooled, and then re-characterized in terms of I-V performance and dynamic impedance. The total noise increase predicted for CrIS after 7-years in orbit is less than 1%.