Publications

Counterfeit microelectronics present a significant challenge to commercial and defense supply chains. Many modern anti-counterfeit strategies rely on manufacturer cooperation to include additional identification components. We instead propose Side Channel Authenticity Discriminant Analysis (SICADA) to leverage physical phenomena manifesting from device operation to match suspect parts to a class of authentic parts. This paper examines the extent that power dissipation information can be used to separate unique classes of devices. A methodology for distinguishing device types is presented and tested on both simulation data of a custom circuit and empirical measurements of Microchip dsPIC33F microcontrollers. Experimental results show that power side channels contain significant distinguishing information to identify parts as authentic or suspect counterfeit.

The minimum energy point of an integrated circuit (IC) is defined as the value of the supply voltage at which the energy per operation of the circuit is minimized. Several factors influence what the value of this voltage can be, including the topology of the circuit itself, the input activity factor, and the process technology in which the circuit is implemented. For application-specific ICs (ASICs), the minimum energy point usually occurs at a subthreshold supply voltage. Advances in subthreshold circuit design now permit correct circuit operation at, or even below, the minimum energy point. Since energy consumption is proportional to the square of the supply voltage, circuit design techniques and process technology choices that reduce the minimum energy point inherently improve the energy efficiency of ICs. Previous research has shown that optimizing process technology for subthreshold operation can improve IC energy efficiency. This, coupled with the energy efficiency advantages offered by fully-depleted silicon-on-insulator (FDSOI) processes, have led to the development of a subthreshold-optimized FDSOI process at MIT Lincoln Laboratory (MITLL) called xLP (Extreme Low Power). However, to date there has not been a quantitative estimate of the energy efficiency benefit of xLP or other analagous technology for complex digital circuits. This paper will show via simulation that the xLP process technology enables energy efficiency improvements that exceed that of process scaling by one generation. Specifically, the process is shown to improve power delay product by 57% vs. the IBM 90nm low power bulk process, and by 9% vs. the IBM 65 nm low power bulk technology at 0.3V.

An asynchronous readout integrated circuit (ROIC) has been developed for hybridization to a 32x32 array of single-photon sensitive avalanche photodiodes (APDs). The asynchronous ROIC is capable of simultaneous detection and readout of photon times of arrival, with no array blind time. Each pixel in the array is independently operated by a finite state machine that actively quenches an APD upon a photon detection event, and re-biases the device into Geiger mode after a programmable hold-off time. While an individual APD is in hold-off mode, other elements in the array are biased and available to detect photons. This approach enables high pixel refresh frequency (PRF), making the device suitable for applications including optical communications and frequency-agile ladar. A built-in electronic shutter that de-biases the whole array allows the detector to operate in a gated mode or allows for detection to be temporarily disabled. On-chip data reduction reduces the high bandwidth requirements of simultaneous detection and readout. Additional features include programmable single-pixel disable, region of interest processing, and programmable output data rates. State-based on-chip clock gating reduces overall power draw. ROIC operation has been demonstrated with hybridized InP APDs sensitive to 1.06-Mm and 1.55-Mm wavelength, and fully packaged focal plane arrays (FPAs) have been assembled and characterized.