Three-dimensional integration technology for advanced focal planes
December 1, 2009
Conference Paper
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Published in:
Mater. Res. Soc. Symp., Volume 1112, 1-5 December 2008, 1112-E01-02.
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Summary
We have developed a three-dimensional (3D) circuit integration technology that exploits the advantages of silicon-on-insulator (SOI) technology to enable wafer-level stacking and micrometer-scale electrical interconnection of fully fabricated circuit wafers. This paper describes the 3D technology and discusses some of the advanced focal plane arrays that have been built using it.