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A study of crosstalk in a 256 x 256 photon counting imager based on silicon Geiger-mode avalanche photodiodes

April 1, 2015
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Journal Article
Author:
Brian F. Aull
…
Published in:
IEEE Sens. J., Vol. 15, No. 4, April 2015, pp. 2123-32.
Topic:
photonics
R&D area:
R&D group:

Summary

We demonstrate a 256 x 256 passive photon counting imager based on hybridization of back-illuminated silicon Geiger-mode avalanche photodiodes to an all-digital CMOS counting chip. Photon detection efficiencies in the 10%-20% are observed at visible wavelengths. The detection efficiency is currently limited by optical crosstalk that leads to elevation of dark count rates as the bias voltage on the photodiodes is increased. Both the time dependence of dark count activity during a gate time and the spatial structure of dark images were successfully explained using crosstalk-based models.
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Summary

We demonstrate a 256 x 256 passive photon counting imager based on hybridization of back-illuminated silicon Geiger-mode avalanche photodiodes to an all-digital CMOS counting chip. Photon detection efficiencies in the 10%-20% are observed at visible wavelengths. The detection efficiency is currently limited by optical crosstalk that leads to elevation of...

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A study of crosstalk in a 256 x 256 photon counting imager based on silicon Geiger-mode avalanche photodiodes

Development and application of spherically curved charge-coupled device imagers

April 1, 2015
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Journal Article
Author:
James A. Gregory
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Published in:
Appl. Opt., Vol. 54, No. 10, 1 April 2015, pp. 3072-82.
Topic:
optics
R&D area:
R&D group:

Summary

Operation of a CCD imager on a curved focal surface offers advantages to flat focal planes, especially for lightweight, relatively simple optical systems. The first advantage is that the modulation transfer function can approach diffraction-limited performance for a spherical focal surface employed in large field-of-view or large-format imagers. The second advantage is that a curved focal surface maintains more uniform illumination as a function of radius from the field center. Examples of applications of curved imagers, described here, include a small compact imager and the large curved array used in the Space Surveillance Telescope. The operational characteristics and mechanical limits of an imager deformed to a 15 mm radius are also described.
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Summary

Operation of a CCD imager on a curved focal surface offers advantages to flat focal planes, especially for lightweight, relatively simple optical systems. The first advantage is that the modulation transfer function can approach diffraction-limited performance for a spherical focal surface employed in large field-of-view or large-format imagers. The second...

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Development and application of spherically curved charge-coupled device imagers

Development of CCDs for REXIS on OSIRIS-REx

July 24, 2014
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Conference Paper
Author:
Kevin K. Ryu
…
Published in:
SPIE, Vol. 9144, Space Telescopes and Instrumentation 2014: Ultraviolet to Gamma Ray, 22 June 2014, 91444O.
Topic:
optics
R&D area:
R&D group:

Summary

The Regolith x-ray Imaging Spectrometer (REXIS) is a coded-aperture soft x-ray imaging instrument on the OSIRIS-REx spacecraft to be launched in 2016. The spacecraft will fly to and orbit the near-Earth asteroid Bennu, while REXIS maps the elemental distribution on the asteroid using x-ray fluorescence. The detector consists of a 2x2 array of back-illuminated 1kX1k frame transfer CCDs with a flight heritage to Suzaku and Chandra. The back surface has a thing p+-doped layer deposited by molecular-beam epitaxy (MBE) for maximum quantum efficiency and energy resolution at low x-ray energies. The CCDs also feature an integrated optical-blocking filter (OBF) to suppress visible and near-infrared light. The OBF is an aluminum film deposited directly on the CCD back surface and is mechanically more robust and less absorptive of x-rays than the conventional free-standing aluminum-coated polymer films. The CCDs have charge transfer inefficiencies of less than 10^-6, and dark current of le-/pixel/second at the REXIS operating temperature of -60 degrees C. The resulting spectral resolution is 115 eV at 2 KeV. The extinction ratio of the filter is ~10^12 at 625 nm.
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Summary

The Regolith x-ray Imaging Spectrometer (REXIS) is a coded-aperture soft x-ray imaging instrument on the OSIRIS-REx spacecraft to be launched in 2016. The spacecraft will fly to and orbit the near-Earth asteroid Bennu, while REXIS maps the elemental distribution on the asteroid using x-ray fluorescence. The detector consists of a...

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Development of CCDs for REXIS on OSIRIS-REx

Gigahertz (GHz) hard X-ray imaging using fast scintillators

September 26, 2013
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Conference Paper
Author:
Zhehui Wang
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Published in:
SPIE Vol. 8852, Hard X-Ray, Gamma-Ray, and Neutron Detector Physics XV, 26 September 2013, 88521A.
Topic:
optics
R&D area:
R&D group:

Summary

Gigahertz (GHz) imaging technology will be needed at high-luminosity X-ray and charged particle sources. It is plausible to combine fast scintillators with the latest picosecond detectors and GHz electronics for multi-frame hard X-ray imaging and achieve an inter-frame time of elss than 10 ns. The time responses and light yield of LYSO, LaBr3, BaF2 and ZnO are measured using an MCP-PMT detector. Zinc Oxide (ZnO) is an attractive material for fast hard X-ray imaging based on GEANT4 simulations and previous studies, but the measured light yield from the samples is much lower than expected.
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Summary

Gigahertz (GHz) imaging technology will be needed at high-luminosity X-ray and charged particle sources. It is plausible to combine fast scintillators with the latest picosecond detectors and GHz electronics for multi-frame hard X-ray imaging and achieve an inter-frame time of elss than 10 ns. The time responses and light yield...

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Gigahertz (GHz) hard X-ray imaging using fast scintillators

Three-dimensional integration technology for advanced focal planes

December 1, 2009
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Conference Paper
Author:
Craig L. Keast
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Published in:
Mater. Res. Soc. Symp., Volume 1112, 1-5 December 2008, 1112-E01-02.
Topic:
integrated circuit
R&D area:
R&D group:

Summary

We have developed a three-dimensional (3D) circuit integration technology that exploits the advantages of silicon-on-insulator (SOI) technology to enable wafer-level stacking and micrometer-scale electrical interconnection of fully fabricated circuit wafers. This paper describes the 3D technology and discusses some of the advanced focal plane arrays that have been built using it.
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Summary

We have developed a three-dimensional (3D) circuit integration technology that exploits the advantages of silicon-on-insulator (SOI) technology to enable wafer-level stacking and micrometer-scale electrical interconnection of fully fabricated circuit wafers. This paper describes the 3D technology and discusses some of the advanced focal plane arrays that have been built using...

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Three-dimensional integration technology for advanced focal planes

A 4-side tileable back illuminated 3D-integrated Mpixel CMOS image sensor

February 9, 2009
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Conference Paper
Author:
Vyshnavi Suntharalingam
…
Published in:
ISSCC 09, 2009 IEEE Int. Solid-State Circuits Conf., 8-12 February 2009, pp. 38-39.
Topic:
semiconductor (CMOS)
R&D area:
R&D group:

Summary

The dominant trend with conventional image sensors is toward scaled-down pixel sizes to increase spatial resolution and decrease chip size and cost. While highly capable chips, these monolithic image sensors devote substantial perimeter area to signal acquisition and control circuitry and trade off pixel complexity for fill factor. For applications such as wide-area persistent surveillance, reconnaissance, and astronomical sky surveys it is desirable to have simultaneous near-real-time imagery with fast, wide field-of-view coverage. Since the fabrication of a complex large-format sensor on a single piece of silicon is cost and yield-prohibitive and is limited to the wafer size, for these applications many smaller-sized image sensors are tiled together to realize very large arrays. Ideally the tiled image sensor has no missing pixels and the pixel pitch is continuous across the seam to minimize loss of information content. CCD-based imagers have been favored for these large mosaic arrays because of their low noise and high sensitivity, but CMOS-based image sensors bring architectural benefits, including electronic shutters, enhanced radiation tolerance, and higher data-rate digital outputs that are more easily scalable to larger arrays. In this report the first back-illuminated, 1 Mpixel, 3D-integrated CMOS image sensor with 8 mum-pitch 3D via connections. The chip employs a conventional pixel layout and requires 500 mum of perimeter silicon to house the support circuitry and protect the array from saw damage. In this paper we present a back-illuminated 1 Mpixel CMOS image sensor tile that includes a 64-channel vertically integrated ADC chip stack, and requires only a few pixels of silicon perimeter to the pixel array. The tile and system connector design support 4-side abuttability and fast burst data rates.
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Summary

The dominant trend with conventional image sensors is toward scaled-down pixel sizes to increase spatial resolution and decrease chip size and cost. While highly capable chips, these monolithic image sensors devote substantial perimeter area to signal acquisition and control circuitry and trade off pixel complexity for fill factor. For applications...

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A 4-side tileable back illuminated 3D-integrated Mpixel CMOS image sensor

Scaling three-dimensional SOI integrated-circuit technology

October 1, 2007
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Conference Paper
Author:
Chenson K. Chen
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Published in:
2007 IEEE Int. SOI Conf. Proc., 1-4 October 2007, pp. 87-88.
Topic:
integrated circuit
R&D area:
R&D group:

Summary

Introduction At Lincoln Laboratory, we have established a three dimensional (3D) integrated circuit (IC) technology that has been developed and demonstrated over seven designs, bonding two or three active circuit layers or tiers to form monolithically integrated 3D circuits. Key features of our 3DIC technology include fully depleted SOI (FDSOI) circuit fabrication, low-temperature wafer-scale oxide-to-oxide bonding, precision wafer-to-wafer alignment, and dense unrestricted 3D vias interconnecting stacked circuit layers, successfully demonstrated in a large area 8 x 8 mm2 high-3D-via-count 1024 x 1024 visible imager. In this paper, we describe details of our bonding protocol for 150-mm diameter wafers, leading to a 50% increase in oxide-oxide bond strength and demonstration of +--0.5 am wafer-to-wafer alignment accuracy. We have established design rules for our 3DIC technology, have quantified process factors limiting our design-rule 3D via pitch, and have demonstrated next generation 3D vias with a 2x size reduction, stacked 3D vias, a backmetal interconnect process to reduce 2D circuit exclusion zones, and buried oxide (BOX) vias to allow both electrical and thermal substrate connections. All of these improvements will allow us to continue to reduce minimum 3D via pitch and reduce 2D layout limitations, making our 3DIC technology more attractive to a broader range of applications.
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Summary

Introduction At Lincoln Laboratory, we have established a three dimensional (3D) integrated circuit (IC) technology that has been developed and demonstrated over seven designs, bonding two or three active circuit layers or tiers to form monolithically integrated 3D circuits. Key features of our 3DIC technology include fully depleted SOI (FDSOI)...

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Scaling three-dimensional SOI integrated-circuit technology

A wafer-scale 3-D circuit integration technology

October 1, 2006
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Journal Article
Author:
James A. Burns
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Published in:
IEEE Trans. Electron Devices, Vol. 53, No. 10, October 2006, pp. 2507-2516.
Topic:
integrated circuit
R&D area:
R&D group:

Summary

The rationale and development of a wafer-scale three-dimensional (3-D) integrated circuit technology are described. The essential elements of the 3-D technology are integrated circuit fabrication on silicon-on-insulator wafers, precision wafer-wafer alignment using an in-house-developed alignment system, low-temperature wafer-wafer bonding to transfer and stack active circuit layers, and interconnection of the circuit layers with dense-vertical connections with sub-[Omega] 3-D via resistances. The 3-D integration process is described as well as the properties of the four enabling technologies. The wafer-scale 3-D technology imposes constraints on the placement of the first lithographic level in a wafer-stepper process. Control of wafer distortion and wafer bow is required to achieve submicrometer vertical vias. Three-tier digital and analog 3-D circuits were designed and fabricated. The performance characteristics of a 3-D ring oscillator, a 1024 x 1024 visible imager with an 8-um pixel pitch, and a 64 x 64 Geiger-mode laser radar chip are described.
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Summary

The rationale and development of a wafer-scale three-dimensional (3-D) integrated circuit technology are described. The essential elements of the 3-D technology are integrated circuit fabrication on silicon-on-insulator wafers, precision wafer-wafer alignment using an in-house-developed alignment system, low-temperature wafer-wafer bonding to transfer and stack active circuit layers, and interconnection of the...

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A wafer-scale 3-D circuit integration technology

Laser radar imager based on 3D integration of Geiger-mode avalanche photodiodes with two SOI timing circuit layers

February 6, 2006
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Conference Paper
Author:
Brian F. Aull
…
Published in:
ISSCC 2006, IEEE Int. Solid-State Circuits Conf., 6-9 February 2006.
Topic:
ladar
R&D area:
R&D group:

Summary

We have developed focal-plane arrays and laser-radar (ladar) imaging systems based on Geiger-mode avalanche photodiodes (APDs) integrated with high-speed all-digital CMOS timing circuits. A Geiger-mode APD produces a digital pulse upon detection of a single photon. This pulse is used to stop a fast digital counter in the pixel circuit, thereby measuring photon arrival time. This "photon-to-digital conversion" yields quantum-limited sensitivity and noiseless readout, enabling high-performance ladar systems. Previously reported focal planes, based on bump bonding or epoxy bonding the APDs to foundry chips, had coarse (100um) pixel spacing and 0.5ns timing quantization.
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Summary

We have developed focal-plane arrays and laser-radar (ladar) imaging systems based on Geiger-mode avalanche photodiodes (APDs) integrated with high-speed all-digital CMOS timing circuits. A Geiger-mode APD produces a digital pulse upon detection of a single photon. This pulse is used to stop a fast digital counter in the pixel circuit...

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Laser radar imager based on 3D integration of Geiger-mode avalanche photodiodes with two SOI timing circuit layers

Megapixel CMOS image sensor fabricated in three-dimensional integrated circuit technology

June 19, 2005
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Conference Paper
Author:
Vyshnavi Suntharalingam
…
Published in:
2005 IEEE Int. Solid-Stat Circuits Conf. Digest of Technical Papers, Pt.1, 19-25 June 2005, p. 356-357.
Topic:
integrated circuit
R&D area:
R&D group:

Summary

In this paper a 3D integrated 1024x1024, 8um pixel visible image sensor fabricated with oxide-to-oxide wafer bonding and 2-um square 3-D-vias in every pixel is presented. The 150mm wafer technology integrates a low-leakage, deep-depletion, 100% fill factor photodiode layer to a 3.3-V, 0.35-um gate length fully depleted (FD) SOI CMOS readout circuit layer.
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Summary

In this paper a 3D integrated 1024x1024, 8um pixel visible image sensor fabricated with oxide-to-oxide wafer bonding and 2-um square 3-D-vias in every pixel is presented. The 150mm wafer technology integrates a low-leakage, deep-depletion, 100% fill factor photodiode layer to a 3.3-V, 0.35-um gate length fully depleted (FD) SOI CMOS...

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Megapixel CMOS image sensor fabricated in three-dimensional integrated circuit technology
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