Megapixel CMOS image sensor fabricated in three-dimensional integrated circuit technology
June 19, 2005
Conference Paper
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2005 IEEE Int. Solid-Stat Circuits Conf. Digest of Technical Papers, Pt.1, 19-25 June 2005, p. 356-357.
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Summary
In this paper a 3D integrated 1024x1024, 8um pixel visible image sensor fabricated with oxide-to-oxide wafer bonding and 2-um square 3-D-vias in every pixel is presented. The 150mm wafer technology integrates a low-leakage, deep-depletion, 100% fill factor photodiode layer to a 3.3-V, 0.35-um gate length fully depleted (FD) SOI CMOS readout circuit layer.