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MBE back-illuminated silicon Geiger-mode avalanche photodiodes for enhanced ultraviolet response

April 25, 2011
  |
Conference Paper
Author:
Daniel R. Schuette
…
Published in:
SPIE Vol. 8033, Advanced Photon Counting Techniques V, 25 April 2011, 80330D.
Topic:
sensors
R&D area:
R&D group:

Summary

We have demonstrated a wafer-scale back-illumination process for silicon Geiger-mode avalanche photodiode arrays using Molecular Beam Epitaxy (MBE) for backside passivation. Critical to this fabrication process is support of the thin (< 10 um) detector during the MBE growth by oxide-bonding to a full-thickness silicon wafer. This back-illumination process makes it possible to build low-dark-count-rate single-photon detectors with high quantum efficiency extending to deep ultraviolet wavelengths. This paper reviews our process for fabricating MBE back-illuminated silicon Geigermode avalanche photodiode arrays and presents characterization of initial test devices.
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Summary

We have demonstrated a wafer-scale back-illumination process for silicon Geiger-mode avalanche photodiode arrays using Molecular Beam Epitaxy (MBE) for backside passivation. Critical to this fabrication process is support of the thin ( 10 um) detector during the MBE growth by oxide-bonding to a full-thickness silicon wafer. This back-illumination process makes...

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MBE back-illuminated silicon Geiger-mode avalanche photodiodes for enhanced ultraviolet response

Wafer-scale 3D integration of InGaAs image sensors with Si readout circuits

September 28, 2009
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Conference Paper
Author:
Chang-Lee Chen
…
Published in:
3DIC 2009, IEEE Int. Conf. on 3D System Integration, 28-30 September 2009.
Topic:
integrated circuit
R&D area:
R&D group:

Summary

In this work, we modified our wafer-scale 3D integration technique, originally developed for Si, to hybridize InP-based image sensor arrays with Si readout circuits. InGaAs image arrays based on the InGaAs layer grown on InP substrates were fabricated in the same processing line as silicon-on-insulator (SOI) readout circuits. The finished 150-mm-diameter InP wafer was then directly bonded to the SOI wafer and interconnected to the Si readout circuits by 3D vias. A 1024 x 1024 diode array with 8-um pixel size is demonstrated. This work shows the wafer-scale 3D integration of a compound semiconductor with Si.
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Summary

In this work, we modified our wafer-scale 3D integration technique, originally developed for Si, to hybridize InP-based image sensor arrays with Si readout circuits. InGaAs image arrays based on the InGaAs layer grown on InP substrates were fabricated in the same processing line as silicon-on-insulator (SOI) readout circuits. The finished...

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Wafer-scale 3D integration of InGaAs image sensors with Si readout circuits

A 4-side tileable back illuminated 3D-integrated Mpixel CMOS image sensor

February 9, 2009
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Conference Paper
Author:
Vyshnavi Suntharalingam
…
Published in:
ISSCC 09, 2009 IEEE Int. Solid-State Circuits Conf., 8-12 February 2009, pp. 38-39.
Topic:
semiconductor (CMOS)
R&D area:
R&D group:

Summary

The dominant trend with conventional image sensors is toward scaled-down pixel sizes to increase spatial resolution and decrease chip size and cost. While highly capable chips, these monolithic image sensors devote substantial perimeter area to signal acquisition and control circuitry and trade off pixel complexity for fill factor. For applications such as wide-area persistent surveillance, reconnaissance, and astronomical sky surveys it is desirable to have simultaneous near-real-time imagery with fast, wide field-of-view coverage. Since the fabrication of a complex large-format sensor on a single piece of silicon is cost and yield-prohibitive and is limited to the wafer size, for these applications many smaller-sized image sensors are tiled together to realize very large arrays. Ideally the tiled image sensor has no missing pixels and the pixel pitch is continuous across the seam to minimize loss of information content. CCD-based imagers have been favored for these large mosaic arrays because of their low noise and high sensitivity, but CMOS-based image sensors bring architectural benefits, including electronic shutters, enhanced radiation tolerance, and higher data-rate digital outputs that are more easily scalable to larger arrays. In this report the first back-illuminated, 1 Mpixel, 3D-integrated CMOS image sensor with 8 mum-pitch 3D via connections. The chip employs a conventional pixel layout and requires 500 mum of perimeter silicon to house the support circuitry and protect the array from saw damage. In this paper we present a back-illuminated 1 Mpixel CMOS image sensor tile that includes a 64-channel vertically integrated ADC chip stack, and requires only a few pixels of silicon perimeter to the pixel array. The tile and system connector design support 4-side abuttability and fast burst data rates.
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Summary

The dominant trend with conventional image sensors is toward scaled-down pixel sizes to increase spatial resolution and decrease chip size and cost. While highly capable chips, these monolithic image sensors devote substantial perimeter area to signal acquisition and control circuitry and trade off pixel complexity for fill factor. For applications...

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A 4-side tileable back illuminated 3D-integrated Mpixel CMOS image sensor

Reliable large format arrays of Geiger-mode avalanche photodiodes

May 28, 2008
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Conference Paper
Author:
Gary M. Smith
…
Published in:
IPRM 2008, 20th Int. Conf. on Indium Phosphide and Related Materials, 25-29 May 2008.
Topic:
ladar
R&D area:

Summary

The fabrication of reliable InP-based Geigermode avalanche photodiode arrays is described. Arrays of up to 256 x 64 elements have been produced and mated to silicon read-out circuits forming single-photon infrared focal plane imagers for 1.06 and 1.5 mum applications.
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Summary

The fabrication of reliable InP-based Geigermode avalanche photodiode arrays is described. Arrays of up to 256 x 64 elements have been produced and mated to silicon read-out circuits forming single-photon infrared focal plane imagers for 1.06 and 1.5 mum applications.

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Reliable large format arrays of Geiger-mode avalanche photodiodes

Arrays of InP-based avalanche photodiodes for photon counting

July 1, 2007
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Journal Article
Author:
Simon Verghese
…
Published in:
IEEE J. Sel. Top. Quantum Electron., Vol. 13, No. 4, July/August 2007, pp. 870-886.
Topic:
photonics
R&D area:
R&D group:

Summary

Arrays of InP-based avalanche photodiodes (APDs) with InGaAsP absorber regions have been fabricated and characterized in the Geiger mode for photon-counting applications. Measurements of APDs with InGaAsP absorbers optimized for 1.06 um wavelength show dark count rates (DCRs)
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Summary

Arrays of InP-based avalanche photodiodes (APDs) with InGaAsP absorber regions have been fabricated and characterized in the Geiger mode for photon-counting applications. Measurements of APDs with InGaAsP absorbers optimized for 1.06 um wavelength show dark count rates (DCRs)

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Arrays of InP-based avalanche photodiodes for photon counting

Megapixel CMOS image sensor fabricated in three-dimensional integrated circuit technology

June 19, 2005
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Conference Paper
Author:
Vyshnavi Suntharalingam
…
Published in:
2005 IEEE Int. Solid-Stat Circuits Conf. Digest of Technical Papers, Pt.1, 19-25 June 2005, p. 356-357.
Topic:
integrated circuit
R&D area:
R&D group:

Summary

In this paper a 3D integrated 1024x1024, 8um pixel visible image sensor fabricated with oxide-to-oxide wafer bonding and 2-um square 3-D-vias in every pixel is presented. The 150mm wafer technology integrates a low-leakage, deep-depletion, 100% fill factor photodiode layer to a 3.3-V, 0.35-um gate length fully depleted (FD) SOI CMOS readout circuit layer.
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Summary

In this paper a 3D integrated 1024x1024, 8um pixel visible image sensor fabricated with oxide-to-oxide wafer bonding and 2-um square 3-D-vias in every pixel is presented. The 150mm wafer technology integrates a low-leakage, deep-depletion, 100% fill factor photodiode layer to a 3.3-V, 0.35-um gate length fully depleted (FD) SOI CMOS...

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Megapixel CMOS image sensor fabricated in three-dimensional integrated circuit technology
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