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Resonance fluorescence from an artificial atom in squeezed vacuum

July 1, 2016
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Journal Article
Author:
D. M. Toyli
…
Published in:
Phys. Rev. X, Vol. 6, No. 3, July-September 2016, 031004.
Topic:
optics
R&D area:
R&D group:

Summary

We present an experimental realization of resonance fluorescence in squeezed vacuum. We strongly couple microwave-frequency squeezed light to a superconducting artificial atom and detect the resulting fluorescence with high resolution enabled by a broadband traveling-wave parametric amplifier. We investigate the fluorescence spectra in the weak and strong driving regimes, observing up to 3.1 dB of reduction of the fluorescence linewidth below the ordinary vacuum level and a dramatic dependence of the Mollow triplet spectrum on the relative phase of the driving and squeezed vacuum fields. Our results are in excellent agreement with predictions for spectra produced by a two-level atom in squeezed vacuum [Phys. Rev. Lett. 58, 2539 (1987)], demonstrating that resonance fluorescence offers a resource-efficient means to characterize squeezing in cryogenic environments.
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Summary

We present an experimental realization of resonance fluorescence in squeezed vacuum. We strongly couple microwave-frequency squeezed light to a superconducting artificial atom and detect the resulting fluorescence with high resolution enabled by a broadband traveling-wave parametric amplifier. We investigate the fluorescence spectra in the weak and strong driving regimes, observing...

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Resonance fluorescence from an artificial atom in squeezed vacuum

A near-quantum-limited Josephson traveling-wave parametric amplifier

September 3, 2015
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Journal Article
Author:
C. Macklin
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Published in:
Sci., Vol. 350, No. 6258, 16 October 2015,pp. 307-10.
Topic:
optics
R&D area:
R&D group:

Summary

Detecting single photon level signals--carriers of both classical and quantum information--is particularly challenging for low-energy microwave frequency excitations. Here we introduce a superconducting amplifier based on a Josephson junction transmission line. Unlike current standing-wave parametric amplifiers, this traveling wave architecture robustly achieves high gain over a bandwidth of several gigahertz with sufficient dynamic range to read out 20 superconducting qubits. To achieve this performance, we introduce a sub-wavelength resonant phase matching technique that enables the creation of nonlinear microwave devices with unique dispersion relations. We benchmark the amplifier with weak measurements, obtaining a high quantum efficiency of 75% (70% including following amplifier noise). With a flexible design based on compact lumped elements, this Josephson amplifier has broad applicability to microwave metrology and quantum optics.
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Summary

Detecting single photon level signals--carriers of both classical and quantum information--is particularly challenging for low-energy microwave frequency excitations. Here we introduce a superconducting amplifier based on a Josephson junction transmission line. Unlike current standing-wave parametric amplifiers, this traveling wave architecture robustly achieves high gain over a bandwidth of several gigahertz...

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A near-quantum-limited Josephson traveling-wave parametric amplifier

Fabrication process and properties of fully planarized deep-submicron Nb/Al-AlOx/Nb Josephson junctions for VLSI circuits

June 1, 2015
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Journal Article
Author:
Sergey K. Tolpygo
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Published in:
IEEE Trans. Appl. Supercond., Vol. 25, No. 3, June 2015, 1101312.
Topic:
integrated circuit
R&D area:
R&D group:

Summary

A fabrication process for Nb/Al-AlOx/Nb Josephson junctions (JJs) with sizes down to 200 nm has been developed on a 200-mm-wafer tool set typical for CMOS foundry. This process is the core of several nodes of a roadmap for fully-planarized fabrication processes for superconductor integrated circuits with 4, 8, and 10 niobium layers developed at MIT Lincoln Laboratory. The process utilizes 248 nm photolithography, anodization, high-density plasma etching, and chemical mechanical polishing (CMP) for planarization of SiO2 interlayer dielectric. JJ electric properties and statistics such as on-chip and wafer spreads of critical current, Ic, normal-state conductance, GN, and run-to-run reproducibility have been measured on 200-mm wafers over a broad range of JJ diameters from 200 nm to 1500 nm and critical current densities, Jc, from 10 kA/cm^2 to 50 kA/cm^2 where the JJs become self-shunted. Diffraction-limited photolithography of JJs is discussed. A relationship between JJ mask size, JJ size on wafer, and the minimum printable size for coherent and partially coherent illumination has been worked out. The GN and Ic spreads obtained have been found to be mainly caused by variations of the JJ areas and agree with the model accounting for an enhancement of mask errors near the diffraction-limited minimum printable size of JJs. Ic and GN spreads from 0.8% to 3% have been obtained for JJs with sizes form 1500 nm down to 500 nm. The spreads increase to about 8% for 200-nm JJs. Prospects for circuit densities > 10^6 JJ/cm^2 and 193-nm photolithography for JJ definition are discussed.
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Summary

A fabrication process for Nb/Al-AlOx/Nb Josephson junctions (JJs) with sizes down to 200 nm has been developed on a 200-mm-wafer tool set typical for CMOS foundry. This process is the core of several nodes of a roadmap for fully-planarized fabrication processes for superconductor integrated circuits with 4, 8, and 10...

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Fabrication process and properties of fully planarized deep-submicron Nb/Al-AlOx/Nb Josephson junctions for VLSI circuits

Inductance of circuit structures for MIT LL superconductor electronics fabrication process with 8 niobium layers

June 1, 2015
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Journal Article
Author:
Sergey K. Tolpygo
…
Published in:
IEEE Trans. Appl. Supercond., Vol. 25, No. 3, 1 June 2015, 1100905.
Topic:
integrated circuit
R&D area:
R&D group:

Summary

Inductance of superconducting thin-film inductors and structures with linewidth down to 250 nm has been experimentally evaluated. The inductors include various striplines and microstrips, their 90 degree bends and meanders, interlayer vias, etc., typically used in superconducting digital circuits. The circuits have been fabricated by a fully planarized process with 8 niobium layers, developed at MIT Lincoln Laboratory for very-large-scale superconducting integrated circuits. Excellent run-to-run reproducibility and inductance uniformity of better than 1% across 200-mm wafers have been found. It has been found that the inductance per unit length of stripline and microstrip line inductors continues to grow as the inductor linewidth is reduced deep into the submicron range to the widths comparable to the film thickness and magnetic field penetration depth. It is shown that the linewidth reduction does not lead to widening of the parameter spread due to diminishing sensitivity of the inductance to the linewidth and dielectric thickness. The experimental results were compared with numeric inductance extraction using commercial software and freeware, and a good agreement was found for 3-D inductance extractors. Methods of further miniaturization of circuit inductors for achieving circuit densities >10^6 Josephson junctions per cm^2 are discussed.
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Summary

Inductance of superconducting thin-film inductors and structures with linewidth down to 250 nm has been experimentally evaluated. The inductors include various striplines and microstrips, their 90 degree bends and meanders, interlayer vias, etc., typically used in superconducting digital circuits. The circuits have been fabricated by a fully planarized process with...

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Inductance of circuit structures for MIT LL superconductor electronics fabrication process with 8 niobium layers

Driven dynamics and rotary echo of a qubit tunably coupled to a harmonic oscillator

April 27, 2012
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Journal Article
Author:
Simon Gustavsson
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Published in:
Phys. Rev. Lett., Vol. 108, No. 17, 27 April 2012, 170503.
Topic:
quantum
R&D area:
R&D group:

Summary

We have investigated the driven dynamics of a superconducting flux qubit that is tunably coupled to a microwave resonator. We find that the qubit experiences an oscillating field mediated by off-resonant driving of the resonator, leading to strong modifications of the qubit Rabi frequency. This opens an additional noise channel, and we find that low-frequency noise in the coupling parameter causes a reduction of the coherence time during driven evolution. The noise can be mitigated with the rotary-echo pulse sequence, which, for driven systems, is analogous to the Hahn-echo sequence.
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Summary

We have investigated the driven dynamics of a superconducting flux qubit that is tunably coupled to a microwave resonator. We find that the qubit experiences an oscillating field mediated by off-resonant driving of the resonator, leading to strong modifications of the qubit Rabi frequency. This opens an additional noise channel...

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Driven dynamics and rotary echo of a qubit tunably coupled to a harmonic oscillator

Wafer-scale 3D integration of InGaAs image sensors with Si readout circuits

September 28, 2009
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Conference Paper
Author:
Chang-Lee Chen
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Published in:
3DIC 2009, IEEE Int. Conf. on 3D System Integration, 28-30 September 2009.
Topic:
integrated circuit
R&D area:
R&D group:

Summary

In this work, we modified our wafer-scale 3D integration technique, originally developed for Si, to hybridize InP-based image sensor arrays with Si readout circuits. InGaAs image arrays based on the InGaAs layer grown on InP substrates were fabricated in the same processing line as silicon-on-insulator (SOI) readout circuits. The finished 150-mm-diameter InP wafer was then directly bonded to the SOI wafer and interconnected to the Si readout circuits by 3D vias. A 1024 x 1024 diode array with 8-um pixel size is demonstrated. This work shows the wafer-scale 3D integration of a compound semiconductor with Si.
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Summary

In this work, we modified our wafer-scale 3D integration technique, originally developed for Si, to hybridize InP-based image sensor arrays with Si readout circuits. InGaAs image arrays based on the InGaAs layer grown on InP substrates were fabricated in the same processing line as silicon-on-insulator (SOI) readout circuits. The finished...

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Wafer-scale 3D integration of InGaAs image sensors with Si readout circuits

Integration of high-speed surface-channel charge coupled devices into an SOI CMOS process using strong phase shift lithography

February 26, 2008
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Conference Paper
Author:
Jeffrey M. Knecht
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Published in:
SPIE Vol. 6924, Optical Microlithography XXI, 26-27 February 2008, pp. 69244R.
Topic:
semiconductor (CMOS)
R&D area:
R&D group:

Summary

To enable development of novel signal processing circuits, a high-speed surface-channel charge coupled device (CCD) process has been co-integrated with the Lincoln Laboratory 180-nm RF fully depleted silicon-on-insulator (FDSOI) CMOS technology. The CCDs support charge transfer clock speeds in excess of 1 GHz while maintaining high charge transfer efficiency (CTE). Both the CCD and CMOS gates are formed using a single-poly process, with CCD gates isolated by a narrow phase-shift-defined gap. CTE is strongly dependent on tight control of the gap critical dimension (CD). In this paper we review the tradeoffs encountered in the co-integration of the CCD and CMOS technologies. The effect of partial coherence on gap resolution and pattern fidelity is discussed. The impact of asymmetric bias due to phase error and phase shift mask (PSM) sidewall effects is presented, along with adopted mitigation strategies. Issues relating to CMOS pattern fidelity and CD control in the double patterning process are also discussed. Since some signal processing CCD structures involve two-dimensional transfer paths, many required geometries present phase compliance and trim engineering challenges. Approaches for implementing noncompliant geometries, such as T shapes, are described, and the impact of various techniques on electrical performance is discussed.
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Summary

To enable development of novel signal processing circuits, a high-speed surface-channel charge coupled device (CCD) process has been co-integrated with the Lincoln Laboratory 180-nm RF fully depleted silicon-on-insulator (FDSOI) CMOS technology. The CCDs support charge transfer clock speeds in excess of 1 GHz while maintaining high charge transfer efficiency (CTE)...

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Integration of high-speed surface-channel charge coupled devices into an SOI CMOS process using strong phase shift lithography
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