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Fabrication process and properties of fully planarized deep-submicron Nb/Al-AlOx/Nb Josephson junctions for VLSI circuits

Published in:
IEEE Trans. Appl. Supercond., Vol. 25, No. 3, June 2015, 1101312.

Summary

A fabrication process for Nb/Al-AlOx/Nb Josephson junctions (JJs) with sizes down to 200 nm has been developed on a 200-mm-wafer tool set typical for CMOS foundry. This process is the core of several nodes of a roadmap for fully-planarized fabrication processes for superconductor integrated circuits with 4, 8, and 10 niobium layers developed at MIT Lincoln Laboratory. The process utilizes 248 nm photolithography, anodization, high-density plasma etching, and chemical mechanical polishing (CMP) for planarization of SiO2 interlayer dielectric. JJ electric properties and statistics such as on-chip and wafer spreads of critical current, Ic, normal-state conductance, GN, and run-to-run reproducibility have been measured on 200-mm wafers over a broad range of JJ diameters from 200 nm to 1500 nm and critical current densities, Jc, from 10 kA/cm^2 to 50 kA/cm^2 where the JJs become self-shunted. Diffraction-limited photolithography of JJs is discussed. A relationship between JJ mask size, JJ size on wafer, and the minimum printable size for coherent and partially coherent illumination has been worked out. The GN and Ic spreads obtained have been found to be mainly caused by variations of the JJ areas and agree with the model accounting for an enhancement of mask errors near the diffraction-limited minimum printable size of JJs. Ic and GN spreads from 0.8% to 3% have been obtained for JJs with sizes form 1500 nm down to 500 nm. The spreads increase to about 8% for 200-nm JJs. Prospects for circuit densities > 10^6 JJ/cm^2 and 193-nm photolithography for JJ definition are discussed.
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Summary

A fabrication process for Nb/Al-AlOx/Nb Josephson junctions (JJs) with sizes down to 200 nm has been developed on a 200-mm-wafer tool set typical for CMOS foundry. This process is the core of several nodes of a roadmap for fully-planarized fabrication processes for superconductor integrated circuits with 4, 8, and 10...

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Inductance of circuit structures for MIT LL superconductor electronics fabrication process with 8 niobium layers

Summary

Inductance of superconducting thin-film inductors and structures with linewidth down to 250 nm has been experimentally evaluated. The inductors include various striplines and microstrips, their 90 degree bends and meanders, interlayer vias, etc., typically used in superconducting digital circuits. The circuits have been fabricated by a fully planarized process with 8 niobium layers, developed at MIT Lincoln Laboratory for very-large-scale superconducting integrated circuits. Excellent run-to-run reproducibility and inductance uniformity of better than 1% across 200-mm wafers have been found. It has been found that the inductance per unit length of stripline and microstrip line inductors continues to grow as the inductor linewidth is reduced deep into the submicron range to the widths comparable to the film thickness and magnetic field penetration depth. It is shown that the linewidth reduction does not lead to widening of the parameter spread due to diminishing sensitivity of the inductance to the linewidth and dielectric thickness. The experimental results were compared with numeric inductance extraction using commercial software and freeware, and a good agreement was found for 3-D inductance extractors. Methods of further miniaturization of circuit inductors for achieving circuit densities >10^6 Josephson junctions per cm^2 are discussed.
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Summary

Inductance of superconducting thin-film inductors and structures with linewidth down to 250 nm has been experimentally evaluated. The inductors include various striplines and microstrips, their 90 degree bends and meanders, interlayer vias, etc., typically used in superconducting digital circuits. The circuits have been fabricated by a fully planarized process with...

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Reconfigurable RF systems using commercially available digital capacitor arrays

Published in:
38th Annual GOMACTech Conf., 11-14 March 2013.
R&D group:

Summary

Various RF circuit blocks implemented by using commercially available MEMS digital capacitor arrays are presented for reconfigurable RF systems. The designed circuit blocks are impedance-matching network, tunable bandpass filter, and VSWR sensor. The frequency range of the designed circuits is 0.4-4GHz. The MEMS digital capacitor arrays that are employed in the designs have built-in dc-to-dc voltage converter and serial interface significantly simplifying the control circuitry. The RF circuit blocks are suitable to low-cost, high-level of integration, thanks to the commercially available parts and standard RF packaging technologies.
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Summary

Various RF circuit blocks implemented by using commercially available MEMS digital capacitor arrays are presented for reconfigurable RF systems. The designed circuit blocks are impedance-matching network, tunable bandpass filter, and VSWR sensor. The frequency range of the designed circuits is 0.4-4GHz. The MEMS digital capacitor arrays that are employed in...

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