Publications
Waveguide engineering for hybrid Si/III-V lasers and amplifiers
Summary
Summary
Using adiabatic tapers, hybrid silicon / III-V lasers and amplifiers are integrated with conventional thin (t = 0.25 um) silicon waveguides. Amplifiers have ~12 dB intrachip gain, and similar lasers have thresholds of 35 mA.
Vertically stacked RF switches by wafer-scale three-dimensional integration
Summary
Summary
Vertically stacked RF switches implemented by wafer-scale three-dimensional (3D) integration of three completely fabricated silicon-on-insulator wafers are demonstrated. The individual switch performance was maintained through the 3D integration process while the signal path is shortened by vertical interconnects. The footprint of the switch can be shrunk in proportion to the...
SOI circuits powered by embedded solar cell
Summary
Summary
Solar cells embedded in the SOI substrate were successfully used as the sole energy source to power a ring oscillator fabricated using an ultra-low-power fully depleted SOI process on the same wafer. The speed of the ring oscillator increased with increasing light intensity and showed a fastest oscillation with a...
SOI-enabled three-dimensional integrated-circuit technology
Summary
Summary
We have demonstrated a new 3D device interconnect approach, with direct back side via connection to a transistor in a 3D stack, resulting in a reduced 3D footprint by an estimated ~40% as well as potential for lower series resistance. We have demonstrated high yield 3D through-oxide-via (TOV) with a...
Improvement of SOI MOSFET RF performance by implant optimization
Summary
Summary
The characteristics of silicon on insulator MOSFETs are modified to enhance the RF performance by varying channel implants. Without adding new masks or fabrication steps to the standard CMOS process, this approach can be easily applied in standard foundry fabrication. The transconductance, output resistance, and breakdown voltage can be increased...
Channel engineering of SOI MOSFETs for RF applications
Summary
Summary
Channel engineering of SOI MOSFETs is explored by altering ion implantation without adding any new fabrication steps to the standard CMOS process. The effects of implantation on characteristics important for RF applications, such as transconductance, output resistance, breakdown voltage, are compared. Data show that the best overall RF MOSFET has...
Wafer-scale 3D integration of InGaAs image sensors with Si readout circuits
Summary
Summary
In this work, we modified our wafer-scale 3D integration technique, originally developed for Si, to hybridize InP-based image sensor arrays with Si readout circuits. InGaAs image arrays based on the InGaAs layer grown on InP substrates were fabricated in the same processing line as silicon-on-insulator (SOI) readout circuits. The finished...
High-quality 150 nm InP-to-silicon epitaxial transfer for silicon photonic integrated circuits
Summary
Summary
We demonstrate the transfer of the largest (150 mm in diameter) available InP-based epitaxial structure to the silicon-on-insulator substrate through a direct wafer-bonding process. Over 95% bonding yield and a void-free bonding interface was obtained. A multiple quantum-well diode laser structure is well-preserved after bonding, as indicated by the high-resolution...
Characterization of a three-dimensional SOI integrated-circuit technology
Summary
Summary
At Lincoln Laboratory, we have established a three dimensional (3D) integrated circuit (IC) technology that has been developed and demonstrated over eight designs, bonding two or three active circuit layers or tiers to form monolithically integrated 3D circuits. This technology has been used to successfully demonstrate a large-area 8 x...
Scaling three-dimensional SOI integrated-circuit technology
Summary
Summary
Introduction At Lincoln Laboratory, we have established a three dimensional (3D) integrated circuit (IC) technology that has been developed and demonstrated over seven designs, bonding two or three active circuit layers or tiers to form monolithically integrated 3D circuits. Key features of our 3DIC technology include fully depleted SOI (FDSOI)...