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Waveguide engineering for hybrid Si/III-V lasers and amplifiers

Published in:
CLEO: Conf. on Lasers and Electro-Optics, 6-11 June 2012.

Summary

Using adiabatic tapers, hybrid silicon / III-V lasers and amplifiers are integrated with conventional thin (t = 0.25 um) silicon waveguides. Amplifiers have ~12 dB intrachip gain, and similar lasers have thresholds of 35 mA.
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Summary

Using adiabatic tapers, hybrid silicon / III-V lasers and amplifiers are integrated with conventional thin (t = 0.25 um) silicon waveguides. Amplifiers have ~12 dB intrachip gain, and similar lasers have thresholds of 35 mA.

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Vertically stacked RF switches by wafer-scale three-dimensional integration

Published in:
Electron. Lett., Vol. 48, No. 10, 10 May 2012.

Summary

Vertically stacked RF switches implemented by wafer-scale three-dimensional (3D) integration of three completely fabricated silicon-on-insulator wafers are demonstrated. The individual switch performance was maintained through the 3D integration process while the signal path is shortened by vertical interconnects. The footprint of the switch can be shrunk in proportion to the number of tiers it is distributed between, demonstrating the potential of significant size reduction of multiple-throw switches commonly required in many applications.
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Summary

Vertically stacked RF switches implemented by wafer-scale three-dimensional (3D) integration of three completely fabricated silicon-on-insulator wafers are demonstrated. The individual switch performance was maintained through the 3D integration process while the signal path is shortened by vertical interconnects. The footprint of the switch can be shrunk in proportion to the...

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SOI circuits powered by embedded solar cell

Published in:
2011 IEEE SOI Conf., 3-6 October 2011.

Summary

Solar cells embedded in the SOI substrate were successfully used as the sole energy source to power a ring oscillator fabricated using an ultra-low-power fully depleted SOI process on the same wafer. The speed of the ring oscillator increased with increasing light intensity and showed a fastest oscillation with a 4.5 ns stage delay and 0.26 fJ power-delay product. The maximum power generated by the solar cell was 9.6 mW/cm2 with an efficiency of 11.6%.
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Summary

Solar cells embedded in the SOI substrate were successfully used as the sole energy source to power a ring oscillator fabricated using an ultra-low-power fully depleted SOI process on the same wafer. The speed of the ring oscillator increased with increasing light intensity and showed a fastest oscillation with a...

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SOI-enabled three-dimensional integrated-circuit technology

Published in:
2010 IEEE Int. SOI Conf., 11 October 2010.

Summary

We have demonstrated a new 3D device interconnect approach, with direct back side via connection to a transistor in a 3D stack, resulting in a reduced 3D footprint by an estimated ~40% as well as potential for lower series resistance. We have demonstrated high yield 3D through-oxide-via (TOV) with a 40% size reduction to 1.0 ?m and with an associated exclusion zone reduced by a factor of 2, substantially smaller than in bulk-Si 3D through-siliconvia (TSV) approaches. These significant enhancements were demonstrated with our 3D technology based on conventional SOI wafers.
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Summary

We have demonstrated a new 3D device interconnect approach, with direct back side via connection to a transistor in a 3D stack, resulting in a reduced 3D footprint by an estimated ~40% as well as potential for lower series resistance. We have demonstrated high yield 3D through-oxide-via (TOV) with a...

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Improvement of SOI MOSFET RF performance by implant optimization

Published in:
IEEE Microw. Wirel. Compon. Lett., Vol. 20, No. 5, May 2010, pp. 271-273.

Summary

The characteristics of silicon on insulator MOSFETs are modified to enhance the RF performance by varying channel implants. Without adding new masks or fabrication steps to the standard CMOS process, this approach can be easily applied in standard foundry fabrication. The transconductance, output resistance, and breakdown voltage can be increased by eliminating channel and drain extension implants. As a result, the fmax of the modified n-MOSFET with a 150 nm gate length exceeds 120 GHz, showing a 20% improvement over the standard MOSFET for digital circuits on the same wafer.
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Summary

The characteristics of silicon on insulator MOSFETs are modified to enhance the RF performance by varying channel implants. Without adding new masks or fabrication steps to the standard CMOS process, this approach can be easily applied in standard foundry fabrication. The transconductance, output resistance, and breakdown voltage can be increased...

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Channel engineering of SOI MOSFETs for RF applications

Summary

Channel engineering of SOI MOSFETs is explored by altering ion implantation without adding any new fabrication steps to the standard CMOS process. The effects of implantation on characteristics important for RF applications, such as transconductance, output resistance, breakdown voltage, are compared. Data show that the best overall RF MOSFET has no body and drain-extension implants.
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Summary

Channel engineering of SOI MOSFETs is explored by altering ion implantation without adding any new fabrication steps to the standard CMOS process. The effects of implantation on characteristics important for RF applications, such as transconductance, output resistance, breakdown voltage, are compared. Data show that the best overall RF MOSFET has...

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Wafer-scale 3D integration of InGaAs image sensors with Si readout circuits

Summary

In this work, we modified our wafer-scale 3D integration technique, originally developed for Si, to hybridize InP-based image sensor arrays with Si readout circuits. InGaAs image arrays based on the InGaAs layer grown on InP substrates were fabricated in the same processing line as silicon-on-insulator (SOI) readout circuits. The finished 150-mm-diameter InP wafer was then directly bonded to the SOI wafer and interconnected to the Si readout circuits by 3D vias. A 1024 x 1024 diode array with 8-um pixel size is demonstrated. This work shows the wafer-scale 3D integration of a compound semiconductor with Si.
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Summary

In this work, we modified our wafer-scale 3D integration technique, originally developed for Si, to hybridize InP-based image sensor arrays with Si readout circuits. InGaAs image arrays based on the InGaAs layer grown on InP substrates were fabricated in the same processing line as silicon-on-insulator (SOI) readout circuits. The finished...

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High-quality 150 nm InP-to-silicon epitaxial transfer for silicon photonic integrated circuits

Published in:
Electrochem. Solid-State Lett., Vol. 12, No. 4, January 2009, pp. H101-H104.

Summary

We demonstrate the transfer of the largest (150 mm in diameter) available InP-based epitaxial structure to the silicon-on-insulator substrate through a direct wafer-bonding process. Over 95% bonding yield and a void-free bonding interface was obtained. A multiple quantum-well diode laser structure is well-preserved after bonding, as indicated by the high-resolution X-ray diffraction measurement and photoluminescence (PL) map. A bowing of 64.12 um is measured, resulting in a low bonding-induced strain of 17 MPa. PL measurement shows a standard deviation of 1.09% across the entire bonded area with less than 1.1 nm wavelength shift from the as-grown wafer.
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Summary

We demonstrate the transfer of the largest (150 mm in diameter) available InP-based epitaxial structure to the silicon-on-insulator substrate through a direct wafer-bonding process. Over 95% bonding yield and a void-free bonding interface was obtained. A multiple quantum-well diode laser structure is well-preserved after bonding, as indicated by the high-resolution...

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Characterization of a three-dimensional SOI integrated-circuit technology

Published in:
2008 IEEE Int. SOI Conf. Proc., 6 October 2008, pp. 109-110.

Summary

At Lincoln Laboratory, we have established a three dimensional (3D) integrated circuit (IC) technology that has been developed and demonstrated over eight designs, bonding two or three active circuit layers or tiers to form monolithically integrated 3D circuits. This technology has been used to successfully demonstrate a large-area 8 x 8 mm2 high-3D-via-count 1024 x 1024 visible image, a 64 x 64 laser radar focal plane based on single-photon-sensitive avalanche photodiodes, and a 10Gb/s/pin low power interconnect for 3DICs. 3DIC technology in our most recently completed 3D multiproject (3DM2) run includes three active fully-depleted-SOI (FDSOI) circuit tiers, eleven interconnect-metal layers, and dense unrestricted 3D vias interconnecting stacked circuit layers, as shown in Figure 1. While we continue our efforts to scale our 3DIC technology and increase 3D via density, we are also working to improve our understanding of 3D integration impact on transistor and process monitor circuits. In this paper, we describe our process and test results after single tier circuit fabrication as well as after three-tier integration, determine impact of 3D vias on ring oscillator performance, and demonstrate functionality of single and multi-tier circuits of varying complexity.
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Summary

At Lincoln Laboratory, we have established a three dimensional (3D) integrated circuit (IC) technology that has been developed and demonstrated over eight designs, bonding two or three active circuit layers or tiers to form monolithically integrated 3D circuits. This technology has been used to successfully demonstrate a large-area 8 x...

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Scaling three-dimensional SOI integrated-circuit technology

Published in:
2007 IEEE Int. SOI Conf. Proc., 1-4 October 2007, pp. 87-88.

Summary

Introduction At Lincoln Laboratory, we have established a three dimensional (3D) integrated circuit (IC) technology that has been developed and demonstrated over seven designs, bonding two or three active circuit layers or tiers to form monolithically integrated 3D circuits. Key features of our 3DIC technology include fully depleted SOI (FDSOI) circuit fabrication, low-temperature wafer-scale oxide-to-oxide bonding, precision wafer-to-wafer alignment, and dense unrestricted 3D vias interconnecting stacked circuit layers, successfully demonstrated in a large area 8 x 8 mm2 high-3D-via-count 1024 x 1024 visible imager. In this paper, we describe details of our bonding protocol for 150-mm diameter wafers, leading to a 50% increase in oxide-oxide bond strength and demonstration of +--0.5 am wafer-to-wafer alignment accuracy. We have established design rules for our 3DIC technology, have quantified process factors limiting our design-rule 3D via pitch, and have demonstrated next generation 3D vias with a 2x size reduction, stacked 3D vias, a backmetal interconnect process to reduce 2D circuit exclusion zones, and buried oxide (BOX) vias to allow both electrical and thermal substrate connections. All of these improvements will allow us to continue to reduce minimum 3D via pitch and reduce 2D layout limitations, making our 3DIC technology more attractive to a broader range of applications.
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Summary

Introduction At Lincoln Laboratory, we have established a three dimensional (3D) integrated circuit (IC) technology that has been developed and demonstrated over seven designs, bonding two or three active circuit layers or tiers to form monolithically integrated 3D circuits. Key features of our 3DIC technology include fully depleted SOI (FDSOI)...

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