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Cloud computing in tactical environments

Summary

Ground personnel at the tactical edge often lack data and analytics that would increase their effectiveness. To address this problem, this work investigates methods to deploy cloud computing capabilities in tactical environments. Our approach is to identify representative applications and to design a system that spans the software/hardware stack to support such applications while optimizing the use of scarce resources. This paper presents our high-level design and the results of initial experiments that indicate the validity of our approach.
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Summary

Ground personnel at the tactical edge often lack data and analytics that would increase their effectiveness. To address this problem, this work investigates methods to deploy cloud computing capabilities in tactical environments. Our approach is to identify representative applications and to design a system that spans the software/hardware stack to...

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Development of a high-throughput microwave imaging system for concealed weapons detection

Summary

A video-rate microwave imaging aperture for concealed threat detection can serve as a useful tool in securing crowded, high foot traffic environments. Realization of such a system presents two major technical challenges: 1) implementation of an electrically large antenna array for capture of a moving subject, and 2) fast image reconstruction on cost-effective computing hardware. This paper presents a hardware-efficient multistatic array design to address the former challenge, and a compatible fast imaging technique to address the latter. Prototype hardware which forms a partition of an imaging aperture is discussed. Using this hardware, it is shown that the proposed array design can be used to form high-fidelity 3D images, and that the presented image reconstruction technique can form an image of a human-sized domain in ≤ 0.1s with low cost computing hardware.
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Summary

A video-rate microwave imaging aperture for concealed threat detection can serve as a useful tool in securing crowded, high foot traffic environments. Realization of such a system presents two major technical challenges: 1) implementation of an electrically large antenna array for capture of a moving subject, and 2) fast image...

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Scalable prototyping testbed for MMW imager system

Published in:
6th Int. Symp. on Phased Array Systems and Technology, PAST 2016, 18-21 October 2016.

Summary

A prototyping testbed for an experimental millimeter-wave multiple-imput multiple-output (MIMO) radar system for security applications in high foot-traffic areas will be presented. The system is designed for flexible operation at a 10 Hz video rate, enabled by high-speed electronic scanning and real-time signal processing. Overall imaging system costs are reduced by the use of an innovative ultra-sparse multistatic radar solution and a 3-D near-field beamforming image construction technique targeted for low-cost high-throughput GPU processors. The testbed is architected with FPGAs, GPUs, CPU storage, and networking, capable of supporting future growth in capabilities, such as interference suppression & advanced signal processing algorithms, auxiliary sensing modalities, near-sensor analytics, and integration into a system-of-systems security architecture.
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Summary

A prototyping testbed for an experimental millimeter-wave multiple-imput multiple-output (MIMO) radar system for security applications in high foot-traffic areas will be presented. The system is designed for flexible operation at a 10 Hz video rate, enabled by high-speed electronic scanning and real-time signal processing. Overall imaging system costs are reduced...

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In-storage embedded accelerator for sparse pattern processing

Published in:
HPEC 2016: IEEE Conf. on High Performance Extreme Computing, 13-15 September 2016.

Summary

We present a novel architecture for sparse pattern processing, using flash storage with embedded accelerators. Sparse pattern processing on large data sets is the essence of applications such as document search, natural language processing, bioinformatics, subgraph matching, machine learning, and graph processing. One slice of our prototype accelerator is capable of handling up to 1TB of data, and experiments show that it can outperform C/C++ software solutions on a 16-core system at a fraction of the power and cost; an optimized version of the accelerator can match the performance of a 48-core server.
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Summary

We present a novel architecture for sparse pattern processing, using flash storage with embedded accelerators. Sparse pattern processing on large data sets is the essence of applications such as document search, natural language processing, bioinformatics, subgraph matching, machine learning, and graph processing. One slice of our prototype accelerator is capable...

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Novel graph processor architecture

Published in:
Lincoln Laboratory Journal, Vol. 20, No. 1, 2013, pp. 92-104.

Summary

Graph algorithms are increasingly used in applications that exploit large databases. However, conventional processor architectures are hard-pressed to handle the throughput and memory requirements of graph computation. Lincoln Laboratory's graph-processor architecture represents a fundamental rethinking of architectures. It utilizes innovations that include high-bandwidth three-dimensional (3D) communication links, a sparse matrix-based graph instruction set, accelerator-based architecture, a systolic sorter, randomized communications, a cacheless memory system, and 3D packaging.
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Summary

Graph algorithms are increasingly used in applications that exploit large databases. However, conventional processor architectures are hard-pressed to handle the throughput and memory requirements of graph computation. Lincoln Laboratory's graph-processor architecture represents a fundamental rethinking of architectures. It utilizes innovations that include high-bandwidth three-dimensional (3D) communication links, a sparse matrix-based...

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Novel graph processor architecture

Published in:
Lincoln Laboratory Journal, Vol. 20, No. 1, 2013, pp. 92-104.

Summary

Graph algorithms are increasingly used in applications that exploit large databases. However, conventional processor architectures are hard-pressed to handle the throughput and memory requirements of graph computation. Lincoln Laboratory's graph-processor architecture represents a fundamental rethinking of architectures. It utilizes innovations that include high-bandwidth three-dimensional (3D) communication links, a sparse matrix-based graph instruction set, accelerator-based architecture, a systolic sorter, randomized communications, a cacheless memory system, and 3D packaging.
READ LESS

Summary

Graph algorithms are increasingly used in applications that exploit large databases. However, conventional processor architectures are hard-pressed to handle the throughput and memory requirements of graph computation. Lincoln Laboratory's graph-processor architecture represents a fundamental rethinking of architectures. It utilizes innovations that include high-bandwidth three-dimensional (3D) communication links, a sparse matrix-based...

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