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Vertically stacked RF switches by wafer-scale three-dimensional integration

May 10, 2012
  |
Journal Article
Author:
Chang-Lee Chen
…
Published in:
Electron. Lett., Vol. 48, No. 10, 10 May 2012.
Topic:
integrated circuit
R&D area:

Summary

Vertically stacked RF switches implemented by wafer-scale three-dimensional (3D) integration of three completely fabricated silicon-on-insulator wafers are demonstrated. The individual switch performance was maintained through the 3D integration process while the signal path is shortened by vertical interconnects. The footprint of the switch can be shrunk in proportion to the number of tiers it is distributed between, demonstrating the potential of significant size reduction of multiple-throw switches commonly required in many applications.
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Summary

Vertically stacked RF switches implemented by wafer-scale three-dimensional (3D) integration of three completely fabricated silicon-on-insulator wafers are demonstrated. The individual switch performance was maintained through the 3D integration process while the signal path is shortened by vertical interconnects. The footprint of the switch can be shrunk in proportion to the...

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Vertically stacked RF switches by wafer-scale three-dimensional integration

SOI-enabled three-dimensional integrated-circuit technology

October 11, 2010
  |
Conference Paper
Author:
Chenson K. Chen
…
Published in:
2010 IEEE Int. SOI Conf., 11 October 2010.
Topic:
integrated circuit
R&D area:

Summary

We have demonstrated a new 3D device interconnect approach, with direct back side via connection to a transistor in a 3D stack, resulting in a reduced 3D footprint by an estimated ~40% as well as potential for lower series resistance. We have demonstrated high yield 3D through-oxide-via (TOV) with a 40% size reduction to 1.0 ?m and with an associated exclusion zone reduced by a factor of 2, substantially smaller than in bulk-Si 3D through-siliconvia (TSV) approaches. These significant enhancements were demonstrated with our 3D technology based on conventional SOI wafers.
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Summary

We have demonstrated a new 3D device interconnect approach, with direct back side via connection to a transistor in a 3D stack, resulting in a reduced 3D footprint by an estimated ~40% as well as potential for lower series resistance. We have demonstrated high yield 3D through-oxide-via (TOV) with a...

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SOI-enabled three-dimensional integrated-circuit technology

Improvement of SOI MOSFET RF performance by implant optimization

May 1, 2010
  |
Journal Article
Author:
Chang-Lee Chen
…
Published in:
IEEE Microw. Wirel. Compon. Lett., Vol. 20, No. 5, May 2010, pp. 271-273.
Topic:
semiconductor (CMOS)
R&D area:

Summary

The characteristics of silicon on insulator MOSFETs are modified to enhance the RF performance by varying channel implants. Without adding new masks or fabrication steps to the standard CMOS process, this approach can be easily applied in standard foundry fabrication. The transconductance, output resistance, and breakdown voltage can be increased by eliminating channel and drain extension implants. As a result, the fmax of the modified n-MOSFET with a 150 nm gate length exceeds 120 GHz, showing a 20% improvement over the standard MOSFET for digital circuits on the same wafer.
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Summary

The characteristics of silicon on insulator MOSFETs are modified to enhance the RF performance by varying channel implants. Without adding new masks or fabrication steps to the standard CMOS process, this approach can be easily applied in standard foundry fabrication. The transconductance, output resistance, and breakdown voltage can be increased...

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Improvement of SOI MOSFET RF performance by implant optimization

Three-dimensional integration technology for advanced focal planes

December 1, 2009
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Conference Paper
Author:
Craig L. Keast
…
Published in:
Mater. Res. Soc. Symp., Volume 1112, 1-5 December 2008, 1112-E01-02.
Topic:
integrated circuit
R&D area:
R&D group:

Summary

We have developed a three-dimensional (3D) circuit integration technology that exploits the advantages of silicon-on-insulator (SOI) technology to enable wafer-level stacking and micrometer-scale electrical interconnection of fully fabricated circuit wafers. This paper describes the 3D technology and discusses some of the advanced focal plane arrays that have been built using it.
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Summary

We have developed a three-dimensional (3D) circuit integration technology that exploits the advantages of silicon-on-insulator (SOI) technology to enable wafer-level stacking and micrometer-scale electrical interconnection of fully fabricated circuit wafers. This paper describes the 3D technology and discusses some of the advanced focal plane arrays that have been built using...

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Three-dimensional integration technology for advanced focal planes

Channel engineering of SOI MOSFETs for RF applications

October 5, 2009
  |
Conference Paper
Author:
Chang-Lee Chen
…
Published in:
2009 IEEE Int. SOI Conf. Proc., 5 October 2009.
Topic:
semiconductor (CMOS)
R&D area:

Summary

Channel engineering of SOI MOSFETs is explored by altering ion implantation without adding any new fabrication steps to the standard CMOS process. The effects of implantation on characteristics important for RF applications, such as transconductance, output resistance, breakdown voltage, are compared. Data show that the best overall RF MOSFET has no body and drain-extension implants.
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Summary

Channel engineering of SOI MOSFETs is explored by altering ion implantation without adding any new fabrication steps to the standard CMOS process. The effects of implantation on characteristics important for RF applications, such as transconductance, output resistance, breakdown voltage, are compared. Data show that the best overall RF MOSFET has...

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Channel engineering of SOI MOSFETs for RF applications

Wafer-scale 3D integration of InGaAs image sensors with Si readout circuits

September 28, 2009
  |
Conference Paper
Author:
Chang-Lee Chen
…
Published in:
3DIC 2009, IEEE Int. Conf. on 3D System Integration, 28-30 September 2009.
Topic:
integrated circuit
R&D area:
R&D group:

Summary

In this work, we modified our wafer-scale 3D integration technique, originally developed for Si, to hybridize InP-based image sensor arrays with Si readout circuits. InGaAs image arrays based on the InGaAs layer grown on InP substrates were fabricated in the same processing line as silicon-on-insulator (SOI) readout circuits. The finished 150-mm-diameter InP wafer was then directly bonded to the SOI wafer and interconnected to the Si readout circuits by 3D vias. A 1024 x 1024 diode array with 8-um pixel size is demonstrated. This work shows the wafer-scale 3D integration of a compound semiconductor with Si.
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Summary

In this work, we modified our wafer-scale 3D integration technique, originally developed for Si, to hybridize InP-based image sensor arrays with Si readout circuits. InGaAs image arrays based on the InGaAs layer grown on InP substrates were fabricated in the same processing line as silicon-on-insulator (SOI) readout circuits. The finished...

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Wafer-scale 3D integration of InGaAs image sensors with Si readout circuits

A 4-side tileable back illuminated 3D-integrated Mpixel CMOS image sensor

February 9, 2009
  |
Conference Paper
Author:
Vyshnavi Suntharalingam
…
Published in:
ISSCC 09, 2009 IEEE Int. Solid-State Circuits Conf., 8-12 February 2009, pp. 38-39.
Topic:
semiconductor (CMOS)
R&D area:
R&D group:

Summary

The dominant trend with conventional image sensors is toward scaled-down pixel sizes to increase spatial resolution and decrease chip size and cost. While highly capable chips, these monolithic image sensors devote substantial perimeter area to signal acquisition and control circuitry and trade off pixel complexity for fill factor. For applications such as wide-area persistent surveillance, reconnaissance, and astronomical sky surveys it is desirable to have simultaneous near-real-time imagery with fast, wide field-of-view coverage. Since the fabrication of a complex large-format sensor on a single piece of silicon is cost and yield-prohibitive and is limited to the wafer size, for these applications many smaller-sized image sensors are tiled together to realize very large arrays. Ideally the tiled image sensor has no missing pixels and the pixel pitch is continuous across the seam to minimize loss of information content. CCD-based imagers have been favored for these large mosaic arrays because of their low noise and high sensitivity, but CMOS-based image sensors bring architectural benefits, including electronic shutters, enhanced radiation tolerance, and higher data-rate digital outputs that are more easily scalable to larger arrays. In this report the first back-illuminated, 1 Mpixel, 3D-integrated CMOS image sensor with 8 mum-pitch 3D via connections. The chip employs a conventional pixel layout and requires 500 mum of perimeter silicon to house the support circuitry and protect the array from saw damage. In this paper we present a back-illuminated 1 Mpixel CMOS image sensor tile that includes a 64-channel vertically integrated ADC chip stack, and requires only a few pixels of silicon perimeter to the pixel array. The tile and system connector design support 4-side abuttability and fast burst data rates.
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Summary

The dominant trend with conventional image sensors is toward scaled-down pixel sizes to increase spatial resolution and decrease chip size and cost. While highly capable chips, these monolithic image sensors devote substantial perimeter area to signal acquisition and control circuitry and trade off pixel complexity for fill factor. For applications...

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A 4-side tileable back illuminated 3D-integrated Mpixel CMOS image sensor

Characterization of a three-dimensional SOI integrated-circuit technology

October 6, 2008
  |
Conference Paper
Author:
Chenson K. Chen
…
Published in:
2008 IEEE Int. SOI Conf. Proc., 6 October 2008, pp. 109-110.
Topic:
integrated circuit
R&D area:

Summary

At Lincoln Laboratory, we have established a three dimensional (3D) integrated circuit (IC) technology that has been developed and demonstrated over eight designs, bonding two or three active circuit layers or tiers to form monolithically integrated 3D circuits. This technology has been used to successfully demonstrate a large-area 8 x 8 mm2 high-3D-via-count 1024 x 1024 visible image, a 64 x 64 laser radar focal plane based on single-photon-sensitive avalanche photodiodes, and a 10Gb/s/pin low power interconnect for 3DICs. 3DIC technology in our most recently completed 3D multiproject (3DM2) run includes three active fully-depleted-SOI (FDSOI) circuit tiers, eleven interconnect-metal layers, and dense unrestricted 3D vias interconnecting stacked circuit layers, as shown in Figure 1. While we continue our efforts to scale our 3DIC technology and increase 3D via density, we are also working to improve our understanding of 3D integration impact on transistor and process monitor circuits. In this paper, we describe our process and test results after single tier circuit fabrication as well as after three-tier integration, determine impact of 3D vias on ring oscillator performance, and demonstrate functionality of single and multi-tier circuits of varying complexity.
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Summary

At Lincoln Laboratory, we have established a three dimensional (3D) integrated circuit (IC) technology that has been developed and demonstrated over eight designs, bonding two or three active circuit layers or tiers to form monolithically integrated 3D circuits. This technology has been used to successfully demonstrate a large-area 8 x...

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Characterization of a three-dimensional SOI integrated-circuit technology

Integration of high-speed surface-channel charge coupled devices into an SOI CMOS process using strong phase shift lithography

February 26, 2008
  |
Conference Paper
Author:
Jeffrey M. Knecht
…
Published in:
SPIE Vol. 6924, Optical Microlithography XXI, 26-27 February 2008, pp. 69244R.
Topic:
semiconductor (CMOS)
R&D area:
R&D group:

Summary

To enable development of novel signal processing circuits, a high-speed surface-channel charge coupled device (CCD) process has been co-integrated with the Lincoln Laboratory 180-nm RF fully depleted silicon-on-insulator (FDSOI) CMOS technology. The CCDs support charge transfer clock speeds in excess of 1 GHz while maintaining high charge transfer efficiency (CTE). Both the CCD and CMOS gates are formed using a single-poly process, with CCD gates isolated by a narrow phase-shift-defined gap. CTE is strongly dependent on tight control of the gap critical dimension (CD). In this paper we review the tradeoffs encountered in the co-integration of the CCD and CMOS technologies. The effect of partial coherence on gap resolution and pattern fidelity is discussed. The impact of asymmetric bias due to phase error and phase shift mask (PSM) sidewall effects is presented, along with adopted mitigation strategies. Issues relating to CMOS pattern fidelity and CD control in the double patterning process are also discussed. Since some signal processing CCD structures involve two-dimensional transfer paths, many required geometries present phase compliance and trim engineering challenges. Approaches for implementing noncompliant geometries, such as T shapes, are described, and the impact of various techniques on electrical performance is discussed.
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Summary

To enable development of novel signal processing circuits, a high-speed surface-channel charge coupled device (CCD) process has been co-integrated with the Lincoln Laboratory 180-nm RF fully depleted silicon-on-insulator (FDSOI) CMOS technology. The CCDs support charge transfer clock speeds in excess of 1 GHz while maintaining high charge transfer efficiency (CTE)...

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Integration of high-speed surface-channel charge coupled devices into an SOI CMOS process using strong phase shift lithography

Scaling three-dimensional SOI integrated-circuit technology

October 1, 2007
  |
Conference Paper
Author:
Chenson K. Chen
…
Published in:
2007 IEEE Int. SOI Conf. Proc., 1-4 October 2007, pp. 87-88.
Topic:
integrated circuit
R&D area:
R&D group:

Summary

Introduction At Lincoln Laboratory, we have established a three dimensional (3D) integrated circuit (IC) technology that has been developed and demonstrated over seven designs, bonding two or three active circuit layers or tiers to form monolithically integrated 3D circuits. Key features of our 3DIC technology include fully depleted SOI (FDSOI) circuit fabrication, low-temperature wafer-scale oxide-to-oxide bonding, precision wafer-to-wafer alignment, and dense unrestricted 3D vias interconnecting stacked circuit layers, successfully demonstrated in a large area 8 x 8 mm2 high-3D-via-count 1024 x 1024 visible imager. In this paper, we describe details of our bonding protocol for 150-mm diameter wafers, leading to a 50% increase in oxide-oxide bond strength and demonstration of +--0.5 am wafer-to-wafer alignment accuracy. We have established design rules for our 3DIC technology, have quantified process factors limiting our design-rule 3D via pitch, and have demonstrated next generation 3D vias with a 2x size reduction, stacked 3D vias, a backmetal interconnect process to reduce 2D circuit exclusion zones, and buried oxide (BOX) vias to allow both electrical and thermal substrate connections. All of these improvements will allow us to continue to reduce minimum 3D via pitch and reduce 2D layout limitations, making our 3DIC technology more attractive to a broader range of applications.
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Summary

Introduction At Lincoln Laboratory, we have established a three dimensional (3D) integrated circuit (IC) technology that has been developed and demonstrated over seven designs, bonding two or three active circuit layers or tiers to form monolithically integrated 3D circuits. Key features of our 3DIC technology include fully depleted SOI (FDSOI)...

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Scaling three-dimensional SOI integrated-circuit technology
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