Publications
Characterization of a three-dimensional SOI integrated-circuit technology
October 6, 2008
Conference Paper
Published in:
2008 IEEE Int. SOI Conf. Proc., 6 October 2008, pp. 109-110.
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Summary
At Lincoln Laboratory, we have established a three dimensional (3D) integrated circuit (IC) technology that has been developed and demonstrated over eight designs, bonding two or three active circuit layers or tiers to form monolithically integrated 3D circuits. This technology has been used to successfully demonstrate a large-area 8 x 8 mm2 high-3D-via-count 1024 x 1024 visible image, a 64 x 64 laser radar focal plane based on single-photon-sensitive avalanche photodiodes, and a 10Gb/s/pin low power interconnect for 3DICs. 3DIC technology in our most recently completed 3D multiproject (3DM2) run includes three active fully-depleted-SOI (FDSOI) circuit tiers, eleven interconnect-metal layers, and dense unrestricted 3D vias interconnecting stacked circuit layers, as shown in Figure 1. While we continue our efforts to scale our 3DIC technology and increase 3D via density, we are also working to improve our understanding of 3D integration impact on transistor and process monitor circuits. In this paper, we describe our process and test results after single tier circuit fabrication as well as after three-tier integration, determine impact of 3D vias on ring oscillator performance, and demonstrate functionality of single and multi-tier circuits of varying complexity.
Summary
At Lincoln Laboratory, we have established a three dimensional (3D) integrated circuit (IC) technology that has been developed and demonstrated over eight designs, bonding two or three active circuit layers or tiers to form monolithically integrated 3D circuits. This technology has been used to successfully demonstrate a large-area 8 x...
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A 64 x 64-pixel CMOS test chip for the development of large-format ultra-high-speed snapshot imagers
September 1, 2008
Journal Article
Published in:
IEEE J. Solid-State Circuits, Vol. 43, No. 9, September 2008, pp. 1940-1950.
Summary
A 64 x 64-pixel test circuit was designed and fabricated in 0.18- m CMOS technology for investigating high-speed imaging with large-format imagers. Several features are integrated into the circuit architecture to achieve fast exposure times with low-skew and jitter for simultaneous pixel snapshots. These features include an H-tree clock distribution with local and global repeaters, single-edge trigger propagation, local exposure control, and current-steering sampling circuits. To evaluate the circuit performance, test structures are periodically located throughout the 64 x 64-pixel device. Measured devices have exposure times that can be varied between 75 ps to 305 ps with skew times for all pixels less than +-3 ps and jitter that is less than +-1.2 ps rms. Other performance characteristics are a readout noise of approximately 115 e- rms and an upper dynamic range of 310,000 e-.
Summary
A 64 x 64-pixel test circuit was designed and fabricated in 0.18- m CMOS technology for investigating high-speed imaging with large-format imagers. Several features are integrated into the circuit architecture to achieve fast exposure times with low-skew and jitter for simultaneous pixel snapshots. These features include an H-tree clock distribution...
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Integration of high-speed surface-channel charge coupled devices into an SOI CMOS process using strong phase shift lithography
February 26, 2008
Conference Paper
Published in:
SPIE Vol. 6924, Optical Microlithography XXI, 26-27 February 2008, pp. 69244R.
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Summary
To enable development of novel signal processing circuits, a high-speed surface-channel charge coupled device (CCD) process has been co-integrated with the Lincoln Laboratory 180-nm RF fully depleted silicon-on-insulator (FDSOI) CMOS technology. The CCDs support charge transfer clock speeds in excess of 1 GHz while maintaining high charge transfer efficiency (CTE). Both the CCD and CMOS gates are formed using a single-poly process, with CCD gates isolated by a narrow phase-shift-defined gap. CTE is strongly dependent on tight control of the gap critical dimension (CD). In this paper we review the tradeoffs encountered in the co-integration of the CCD and CMOS technologies. The effect of partial coherence on gap resolution and pattern fidelity is discussed. The impact of asymmetric bias due to phase error and phase shift mask (PSM) sidewall effects is presented, along with adopted mitigation strategies. Issues relating to CMOS pattern fidelity and CD control in the double patterning process are also discussed. Since some signal processing CCD structures involve two-dimensional transfer paths, many required geometries present phase compliance and trim engineering challenges. Approaches for implementing noncompliant geometries, such as T shapes, are described, and the impact of various techniques on electrical performance is discussed.
Summary
To enable development of novel signal processing circuits, a high-speed surface-channel charge coupled device (CCD) process has been co-integrated with the Lincoln Laboratory 180-nm RF fully depleted silicon-on-insulator (FDSOI) CMOS technology. The CCDs support charge transfer clock speeds in excess of 1 GHz while maintaining high charge transfer efficiency (CTE)...
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Design approaches for digitally dominated active pixel sensors: leveraging Moore's law scaling in focal plane readout design
January 20, 2008
Conference Paper
Published in:
SPIE Vol. 6900, Quantum Sensing and Nanophotonic Devices V, 20-23 January 2008, 69000W.
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Summary
Although CMOS technology scaling has provided tremendous power and circuit density benefits for innumerable applications, focal plane array (FPA) readouts have largely been left behind due to dynamic range and signal-to-noise considerations. However, if an appropriate pixel front end can be constructed to interface with a mostly digital pixel, it is possible to develop sensor architectures for which performance scales favorably with advancing technology nodes. Although the front-end design must be optimized to interface with a particular detector, the dominant back end architecture provides considerable potential for design reuse. In this work, digitally dominated long wave infrared (LWIR) active pixel sensors with cutoff wavelengths between 9 and 14.5 um are demonstrated. Two ROIC designs are discussed, each fabricated in a 90-nm digital CMOS process and implementing a 256 x 256 pixel array on a 30-um pitch. In one of the implemented designs, the feasibility of implementing a 15-um pixel pitch FPA with a 500 million electron effective well depth, less than 0.5% non-linearity in the target range and a measured NEdT of less than 50 mK at f/4 and 60 K is demonstrated. Simple on-FPA signal processing allows for a much reduced readout bandwidth requirement with these architectures. To demonstrate the potential for commonality that is offered by a digitally dominated architecture, this LWIR sensor design is compared and contrasted with other digital focal plane architectures. Opportunities and challenges for application of this approach to various detector technologies, optical wavelength ranges and systems are discussed.
Summary
Although CMOS technology scaling has provided tremendous power and circuit density benefits for innumerable applications, focal plane array (FPA) readouts have largely been left behind due to dynamic range and signal-to-noise considerations. However, if an appropriate pixel front end can be constructed to interface with a mostly digital pixel, it...
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Arrays of InP-based avalanche photodiodes for photon counting
July 1, 2007
Journal Article
Published in:
IEEE J. Sel. Top. Quantum Electron., Vol. 13, No. 4, July/August 2007, pp. 870-886.
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Arrays of InP-based avalanche photodiodes (APDs) with InGaAsP absorber regions have been fabricated and characterized in the Geiger mode for photon-counting applications. Measurements of APDs with InGaAsP absorbers optimized for 1.06 um wavelength show dark count rates (DCRs)
Summary
Arrays of InP-based avalanche photodiodes (APDs) with InGaAsP absorber regions have been fabricated and characterized in the Geiger mode for photon-counting applications. Measurements of APDs with InGaAsP absorbers optimized for 1.06 um wavelength show dark count rates (DCRs)
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The digital focal plane array (DFPA) architecture for data processing "on-chip"
February 5, 2007
Conference Paper
Published in:
2007 Meeting of the Military Sensing Symposia (MSS) Specialty Group on Camouflage, Concealment & Deception; Passive Sensors; Detectors; and Materials, 5-9 February 2007.
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Summary
The digital focal plane array (DFPA) project seeks to develop readout integrated circuits (ROICs) utilizing aggressively scaled and commercially available CMOS. Along with focal plane scaling and readout robustness benefits, the DFPA architecture provides a very simple way to implement processing algorithms directly on image data, in real-time, and prior to read-out of the data to an external digitizer or computer. In principle, almost any linear image processing filter kernel can be convolved with the scene image prior to readout. The useful size of the filter kernel is only limited by the size of the DFPA. Time domain filters can also be implemented on the ROIC to accomplish digital time domain integration (TDI) or change detection algorithms. The unique architecture can achieve the processing capability without the use of traditional digital adders or multipliers, like those used in most signal processors. Instead, a DFPA manipulates sequential digital counters under every pixel in a unique way to achieve the desired functionality. A non-addressable readout scheme is used for data transfer in four possible directions across the array. Although we are currently targeting longwave infrared (LWIR) applications, the approach can be potentially applied to any imaging application in any band.
Summary
The digital focal plane array (DFPA) project seeks to develop readout integrated circuits (ROICs) utilizing aggressively scaled and commercially available CMOS. Along with focal plane scaling and readout robustness benefits, the DFPA architecture provides a very simple way to implement processing algorithms directly on image data, in real-time, and prior...
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Lincoln Laboratory high-speed solid-state imager technology
September 17, 2006
Conference Paper
Published in:
SPIE Vol. 6279, 27th Int. Congress on High-Speed Photography and Photonics, 17-22 September 2006, 62791K.
Summary
Massachusetts Institute of Technology, Lincoln Laboratory (MIT LL) has been developing both continuous and burst solid-state focal-plane-array technology for a variety of high-speed imaging applications. For continuous imaging, a 128 ¿ 128-pixel charge coupled device (CCD) has been fabricated with multiple output ports for operating rates greater than 10,000 frames per second with readout noise of less than 10 e- rms. An electronic shutter has been integrated into the pixels of the back-illuminated (BI) CCD imagers that give snapshot exposure times of less than 10 ns. For burst imaging, a 5 cm x 5 cm, 512 x 512-element, multi-frame CCD imager that collects four sequential image frames at megahertz rates has been developed for the Los Alamos National Laboratory Dual Axis Radiographic Hydrodynamic Test (DARHT) facility. To operate at fast frame rates with high sensitivity, the imager uses the same electronic shutter technology as the continuously framing 128 x 128 CCD imager. The design concept and test results are described for the burst-frame-rate imager. Also discussed is an evolving solid-state imager technology that has interesting characteristics for creating large-format x-ray detectors with ultra-short exposure times (100 to 300 ps). The detector will consist of CMOS readouts for high speed sampling (tens of picoseconds transistor switching times) that are bump bonded to deep-depletion silicon photodiodes. A 64 x 64-pixel CMOS test chip has been designed, fabricated and characterized to investigate the feasibility of making large-format detectors with short, simultaneous exposure times.
Summary
Massachusetts Institute of Technology, Lincoln Laboratory (MIT LL) has been developing both continuous and burst solid-state focal-plane-array technology for a variety of high-speed imaging applications. For continuous imaging, a 128 ¿ 128-pixel charge coupled device (CCD) has been fabricated with multiple output ports for operating rates greater than 10,000 frames...
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Megapixel CMOS image sensor fabricated in three-dimensional integrated circuit technology
June 19, 2005
Conference Paper
Published in:
2005 IEEE Int. Solid-Stat Circuits Conf. Digest of Technical Papers, Pt.1, 19-25 June 2005, p. 356-357.
Summary
In this paper a 3D integrated 1024x1024, 8um pixel visible image sensor fabricated with oxide-to-oxide wafer bonding and 2-um square 3-D-vias in every pixel is presented. The 150mm wafer technology integrates a low-leakage, deep-depletion, 100% fill factor photodiode layer to a 3.3-V, 0.35-um gate length fully depleted (FD) SOI CMOS readout circuit layer.
Summary
In this paper a 3D integrated 1024x1024, 8um pixel visible image sensor fabricated with oxide-to-oxide wafer bonding and 2-um square 3-D-vias in every pixel is presented. The 150mm wafer technology integrates a low-leakage, deep-depletion, 100% fill factor photodiode layer to a 3.3-V, 0.35-um gate length fully depleted (FD) SOI CMOS...
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Investigation of the physical and practical limits of dense-only phase shift lithography for circuit feature definition
October 1, 2002
Journal Article
Published in:
J. Microlith., Microfab., Microsyst., Vol. 1, No. 3, October 2002, pp. 243-252.
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Summary
The rise of low- k1 optical lithography in integrated circuit manufacturing has introduced new questions concerning the physical and practical limits of particular subwavelength resolution-enhanced imaging approaches. For a given application, trade-offs between mask complexity, design cycle time, process latitude and process throughput must be well understood. It has recently been shown that a dense-only phase shifting mask (PSM) approach can be applied to technology nodes approaching the physical limits of strong PSM with no proximity effects. Such an approach offers the benefits of reduced mask complexity and design cycle time, at the expense of decreased process throughput and limited design flexibility. In particular, dense-only methods offer k1,0.3, thus enabling 90 nm node lithography with high-numerical aperture 248 nm exposure systems. We present the results of experiments, simulations, and analysis designed to explore the trade-offs inherent in dense-only phase shift lithography. Gate and contact patterns corresponding to various fully scaled circuits are presented, and the relationship between process complexity and design latitude is discussed. Particular attention is given to approaches for obtaining gate features in both the horizontal and vertical orientation. Since semiconductor investment is dependent on cost amortization, the applicability of these methods is also considered in terms of production volume.
Summary
The rise of low- k1 optical lithography in integrated circuit manufacturing has introduced new questions concerning the physical and practical limits of particular subwavelength resolution-enhanced imaging approaches. For a given application, trade-offs between mask complexity, design cycle time, process latitude and process throughput must be well understood. It has recently...
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