Publications

Refine Results

(Filters Applied) Clear All

Dynamic response of an electronically shuttered CCD imager

June 1, 2004
  |
Journal Article
Author:
Dennis D. Rathman
…
Published in:
IEEE. Trans. Electron Devices, Vol. 51, No. 6, June 2004, pp. 864-869.
Topic:
sensors
R&D area:
R&D group:

Summary

The dynamic response of an electronically shuttered charge-coupled device (CCD) imager to nanosecond voltage pulses has been investigated. Measurements show that the shutter can be dynamically opened and closed in nanosecond times. For the shutter opening, simulations indicate that the collection of photoelectrons occurs in times much shorter than that needed to form the steady-state depletion region under the CCD well. In addition, the shutter closing occurs faster than the reconstitution of the p-buried (shutter) layer. Simulations further indicate that electric fields created in the neutral substrate by the shutter clocks enable photogenerated charge collection/rejection on nanosecond time scales despite the fact that the depletion-region formation and collapse take much longer times.
READ LESS

Summary

The dynamic response of an electronically shuttered charge-coupled device (CCD) imager to nanosecond voltage pulses has been investigated. Measurements show that the shutter can be dynamically opened and closed in nanosecond times. For the shutter opening, simulations indicate that the collection of photoelectrons occurs in times much shorter than that...

READ MORE
Dynamic response of an electronically shuttered CCD imager

High-fill-factor, burst-frame-rate charge-coupled device

August 3, 2003
  |
Conference Paper
Author:
Robert K. Reich
…
Published in:
SPIE Vol. 5210, Ultrahigh- and High-Speed Photography, Photonics, and Videography, 3-8 August 2003, pp. 95-104.
Topic:
electronics
R&D area:
R&D group:

Summary

A 512x512-element, multi-frame charge-coupled device (CCD) has been developed for collecting four sequential image frames at megahertz rates. To operate at fast frame rates with high sensitivity, the imager uses an electronic shutter technology developed for back-illuminated CCDs. Device-level simulations were done to estimate the CCD collection well spaces for sub-microsecond photoelectron collection times. Also required for the high frame rates were process enhancements that included metal strapping of the polysilicon gate electrodes and a second metal layer. Tests on finished back-illuminated CCD imagers have demonstrated sequential multi-frame capture capability with integration intervals in the hundreds of nanoseconds range.
READ LESS

Summary

A 512x512-element, multi-frame charge-coupled device (CCD) has been developed for collecting four sequential image frames at megahertz rates. To operate at fast frame rates with high sensitivity, the imager uses an electronic shutter technology developed for back-illuminated CCDs. Device-level simulations were done to estimate the CCD collection well spaces for...

READ MORE
High-fill-factor, burst-frame-rate charge-coupled device

Investigation of the physical and practical limits of dense-only phase shift lithography for circuit feature definition

October 1, 2002
  |
Journal Article
Author:
Brian M. Tyrrell
…
Published in:
J. Microlith., Microfab., Microsyst., Vol. 1, No. 3, October 2002, pp. 243-252.
Topic:
integrated circuit
R&D area:
R&D group:

Summary

The rise of low- k1 optical lithography in integrated circuit manufacturing has introduced new questions concerning the physical and practical limits of particular subwavelength resolution-enhanced imaging approaches. For a given application, trade-offs between mask complexity, design cycle time, process latitude and process throughput must be well understood. It has recently been shown that a dense-only phase shifting mask (PSM) approach can be applied to technology nodes approaching the physical limits of strong PSM with no proximity effects. Such an approach offers the benefits of reduced mask complexity and design cycle time, at the expense of decreased process throughput and limited design flexibility. In particular, dense-only methods offer k1,0.3, thus enabling 90 nm node lithography with high-numerical aperture 248 nm exposure systems. We present the results of experiments, simulations, and analysis designed to explore the trade-offs inherent in dense-only phase shift lithography. Gate and contact patterns corresponding to various fully scaled circuits are presented, and the relationship between process complexity and design latitude is discussed. Particular attention is given to approaches for obtaining gate features in both the horizontal and vertical orientation. Since semiconductor investment is dependent on cost amortization, the applicability of these methods is also considered in terms of production volume.
READ LESS

Summary

The rise of low- k1 optical lithography in integrated circuit manufacturing has introduced new questions concerning the physical and practical limits of particular subwavelength resolution-enhanced imaging approaches. For a given application, trade-offs between mask complexity, design cycle time, process latitude and process throughput must be well understood. It has recently...

READ MORE
Investigation of the physical and practical limits of dense-only phase shift lithography for circuit feature definition

High-speed, electronically shuttered solid-state imager technology

July 8, 2002
  |
Conference Paper
Author:
Robert K. Reich
…
Published in:
Rev. Sci. Instrum. Vol. 74, No. 3, Pt. II, March 2003, pp. 2027-2031 (Proceedings of the 14th Topical Conference on High-Temperature Plasma Diagnostics, 8-11 July 2002)
Topic:
electronics
R&D area:
R&D group:

Summary

Electronically shuttered solid-state imagers are being developed for high-speed imaging applications. A 5 cmx5 cm, 512x512-element, multiframe charge-coupled device (CCD) imager has been fabricated for the Los Alamos National Laboratory DARHT facility that collects four sequential image frames at megahertz rates. To operate at fast frame rates with high sensitivity, the imager uses an electronic shutter technology designed for back-illuminated CCDs. The design concept and test results are described for the burst-frame-rate imager. Also discussed is an evolving solid-state imager technology that has interesting characteristics for creating large-format x-ray detectors with short integration times (100 ps to 1 ns). Proposed device architectures use CMOS technology for high speed sampling (tens of picoseconds transistor switching times). Techniques for parallel clock distribution, that triggers the sampling of x-ray photoelectrons, will be described that exploit features of CMOS technology.
READ LESS

Summary

Electronically shuttered solid-state imagers are being developed for high-speed imaging applications. A 5 cmx5 cm, 512x512-element, multiframe charge-coupled device (CCD) imager has been fabricated for the Los Alamos National Laboratory DARHT facility that collects four sequential image frames at megahertz rates. To operate at fast frame rates with high sensitivity...

READ MORE
High-speed, electronically shuttered solid-state imager technology

Broadband (200-1000 nm) back-illuminated ccd imagers

June 16, 2002
  |
Conference Paper
Author:
Barry E. Burke
…
Published in:
Scientific Detectors Workshop 2002, 16-22 June 2002.p. 41-50.
Topic:
optics
R&D area:
R&D group:

Summary

Improved and stable blue/UV quantum efficiency has been demonstrated on 2Kx4K imagers using molecular-beam epitaxy to create a thin doped layer on the back surface. Quantum efficiency data on thick (40-50 pm) imagers with single and dual-layer anti-reflection coatings is presented that demonstrates high and broadband response. Measurements of the optical point-spread response show the devices to be fully depleted with good response across a broad spectrum, but interesting features appear in the near-IR as a result of deeply penetrating light being scattered off the surface structure of the CCD.
READ LESS

Summary

Improved and stable blue/UV quantum efficiency has been demonstrated on 2Kx4K imagers using molecular-beam epitaxy to create a thin doped layer on the back surface. Quantum efficiency data on thick (40-50 pm) imagers with single and dual-layer anti-reflection coatings is presented that demonstrates high and broadband response. Measurements of the...

READ MORE
Broadband (200-1000 nm) back-illuminated ccd imagers

Geiger-mode avalanche photodiodes for three-dimensional imaging

January 1, 2002
  |
Journal Article
Author:
Brian F. Aull
…
Published in:
Lincoln Laboratory Journal, Vol. 13, No. 2, 2002, pp. 335-350.
Topic:
ladar
R&D area:
R&D group:

Summary

We discuss the properties of Geiger-mode avalanche photodiodes (APDs) and their use in developing an imaging laser radar (ladar). This type of photodetector gives a fast electrical pulse in response to the detection of even a single photon, allowing for sub-nsec-precision photon-flight-time measurement. We present ongoing work at Lincoln Laboratory on three-dimensional (3D) imaging with arrays of these diodes, and the integration of the arrays with fast complementary metal-oxide semiconductor (CMOS) digital timing circuits.
READ LESS

Summary

We discuss the properties of Geiger-mode avalanche photodiodes (APDs) and their use in developing an imaging laser radar (ladar). This type of photodetector gives a fast electrical pulse in response to the detection of even a single photon, allowing for sub-nsec-precision photon-flight-time measurement. We present ongoing work at Lincoln Laboratory...

READ MORE
Geiger-mode avalanche photodiodes for three-dimensional imaging

Silicon-on-insulator-based single-chip image sensors: low-voltage scientific imaging

January 1, 2002
  |
Conference Paper
Author:
Vyshnavi Suntharalingam
…
Published in:
Experimental Astronomy, Vol. 14, No. 2, 2002, pp. 91-98.
Topic:
sensors
R&D area:
R&D group:

Summary

A low-voltage (
READ LESS

Summary

A low-voltage (

READ MORE
Silicon-on-insulator-based single-chip image sensors: low-voltage scientific imaging

Monolithic 3.3V CCD/SOI-CMOS Imager Technology

December 10, 2000
  |
Conference Paper
Author:
Vyshnavi Suntharalingam
…
Published in:
IEEE Int. Eelctron Devices Mtg., 10-13 December 2000, pp. 30.3.1-30.3.4.
Topic:
semiconductor (CMOS)
R&D area:
R&D group:

Summary

We have developed a merged CCD/SOI-CMOS technology that enables the fabrication of monolithic, low-power imaging systems on a chip. The CCD's, fabricated in the bulk handle wafer, have charge-transfer inefficiencies of about 1x10(-5) and well capacities of more than 100,000 electrons with 3.3-V clocks and 8x8um pixels. Fully depleted 0.35pm SOI-CMOS ring oscillators have stage delay of 48ps at 3.3V. We demonstrate for the first time an integrated image sensor with charge-domain A/D conversion and on-chip clocking.
READ LESS

Summary

We have developed a merged CCD/SOI-CMOS technology that enables the fabrication of monolithic, low-power imaging systems on a chip. The CCD's, fabricated in the bulk handle wafer, have charge-transfer inefficiencies of about 1x10(-5) and well capacities of more than 100,000 electrons with 3.3-V clocks and 8x8um pixels. Fully depleted 0.35pm...

READ MORE
Monolithic 3.3V CCD/SOI-CMOS Imager Technology

SOI wafer selection for CCD/SOI-CMOS technology [Abstract]

October 2, 2000
  |
Conference Paper
Author:
Vyshnavi Suntharalingam
…
Published in:
2000 IEEE Int. SOI Conf. Proc., 2-5 October 2000, pp. 136-137.
Topic:
semiconductor (CMOS)
R&D area:
R&D group:

Summary

We have developed a process that monolithically integrates fully depleted SOI CMOS (FDSOI) with high-performance CCD image sensors. This integrated technology that enables charged-coupled devices (CCD's) to be in close proximity to, yet isolated from, FDSOI circuits. This approach exploits both the advantages of FDSOI (fast, low-power CMOS with potentially enhanced radiation performance) and those of CCD's (high quantum efftciency, low noise, and architectural flexibility). This 3.3 V, 0.3 mu m CCD/FDSOI-CMOS technology thus enables fabrication of low-power, compact imaging systems. Material requirements for CCD imagers are perhaps the most stringent of any device and require special attention to the quality of the bulk or handle wafer. We report here characterization of various SOI handle wafers for use in fabrication of bulk imaging devices.
READ LESS

Summary

We have developed a process that monolithically integrates fully depleted SOI CMOS (FDSOI) with high-performance CCD image sensors. This integrated technology that enables charged-coupled devices (CCD's) to be in close proximity to, yet isolated from, FDSOI circuits. This approach exploits both the advantages of FDSOI (fast, low-power CMOS with potentially...

READ MORE
SOI wafer selection for CCD/SOI-CMOS technology [Abstract]

Soft-x-ray CCD imagers for AXAF

October 1, 1997
  |
Journal Article
Author:
Barry E. Burke
…
Published in:
IEEE Trans. Electron Devices, Vol. 44, No. 10, October 1997, pp. 1633-1642.
Topic:
sensors
R&D area:
R&D group:

Summary

We describe the key features and performance data of a 1024 x 1026-pixel frame-transfer imager for use as a soft-x-ray detector on the NASA X-ray observatory Advanced X-ray Astrophysics Facility (AXAF). The four-port device features a floating-diffusion output circuit with a responsivity of 20/spl mu/V/e/sup -/ and noise of about 2 e/sup -/ at a 100-kHz data rate. Techniques for achieving the low sense-node capacitance of 5 fF are described. The CCD is fabricated on high-resistivity p-type silicon for deep depletion and includes narrow potential troughs for transfer inefficiencies of around 10/sup -7/ (ten to the negative 7). To achieve good sensitivity at energies below 1 keV, we have developed a back-illumination process that features low recombination losses at the back surface and has produced efficiencies of about 0.7 at 277 eV (carbon K/spl alpha/).
READ LESS

Summary

We describe the key features and performance data of a 1024 x 1026-pixel frame-transfer imager for use as a soft-x-ray detector on the NASA X-ray observatory Advanced X-ray Astrophysics Facility (AXAF). The four-port device features a floating-diffusion output circuit with a responsivity of 20/spl mu/V/e/sup -/ and noise of about...

READ MORE
Soft-x-ray CCD imagers for AXAF
61-70 of 73